/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/i2caux_interface.h"
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#include "engine.h"
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#include "i2c_engine.h"
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#include "i2c_hw_engine.h"
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/*
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* Header of this unit
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*/
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#include "i2c_generic_hw_engine.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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/*
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* This unit
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*/
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/*
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* @brief
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* Cast 'struct i2c_hw_engine *'
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* to 'struct i2c_generic_hw_engine *'
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*/
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#define FROM_I2C_HW_ENGINE(ptr) \
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container_of((ptr), struct i2c_generic_hw_engine, base)
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/*
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* @brief
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* Cast 'struct i2c_engine *'
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* to 'struct i2c_generic_hw_engine *'
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*/
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#define FROM_I2C_ENGINE(ptr) \
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FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
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/*
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* @brief
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* Cast 'struct engine *'
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* to 'struct i2c_generic_hw_engine *'
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*/
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#define FROM_ENGINE(ptr) \
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FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
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enum i2caux_engine_type dal_i2c_generic_hw_engine_get_engine_type(
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const struct engine *engine)
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{
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return I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW;
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}
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/*
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* @brief
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* Single transaction handling.
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* Since transaction may be bigger than HW buffer size,
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* it divides transaction to sub-transactions
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* and uses batch transaction feature of the engine.
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*/
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bool dal_i2c_generic_hw_engine_submit_request(
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struct engine *engine,
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struct i2caux_transaction_request *i2caux_request,
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bool middle_of_transaction)
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{
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struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
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struct i2c_hw_engine *base = &hw_engine->base;
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uint32_t max_payload_size =
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base->funcs->get_hw_buffer_available_size(base);
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bool initial_stop_bit = !middle_of_transaction;
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struct i2c_generic_transaction_attributes attributes;
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enum i2c_channel_operation_result operation_result =
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I2C_CHANNEL_OPERATION_FAILED;
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bool result = false;
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/* setup transaction initial properties */
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uint8_t address = i2caux_request->payload.address;
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uint8_t *current_payload = i2caux_request->payload.data;
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uint32_t remaining_payload_size = i2caux_request->payload.length;
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bool first_iteration = true;
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if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
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attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_READ;
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else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
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attributes.action = I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
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else {
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
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return false;
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}
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/* Do batch transaction.
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* Divide read/write data into payloads which fit HW buffer size.
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* 1. Single transaction:
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* start_bit = 1, stop_bit depends on session state, ack_on_read = 0;
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* 2. Start of batch transaction:
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* start_bit = 1, stop_bit = 0, ack_on_read = 1;
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* 3. Middle of batch transaction:
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* start_bit = 0, stop_bit = 0, ack_on_read = 1;
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* 4. End of batch transaction:
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* start_bit = 0, stop_bit depends on session state, ack_on_read = 0.
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* Session stop bit is set if 'middle_of_transaction' = 0. */
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while (remaining_payload_size) {
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uint32_t current_transaction_size;
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uint32_t current_payload_size;
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bool last_iteration;
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bool stop_bit;
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/* Calculate current transaction size and payload size.
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* Transaction size = total number of bytes in transaction,
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* including slave's address;
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* Payload size = number of data bytes in transaction. */
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if (first_iteration) {
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/* In the first sub-transaction we send slave's address
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* thus we need to reserve one byte for it */
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current_transaction_size =
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(remaining_payload_size > max_payload_size - 1) ?
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max_payload_size :
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remaining_payload_size + 1;
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current_payload_size = current_transaction_size - 1;
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} else {
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/* Second and further sub-transactions will have
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* entire buffer reserved for data */
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current_transaction_size =
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(remaining_payload_size > max_payload_size) ?
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max_payload_size :
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remaining_payload_size;
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current_payload_size = current_transaction_size;
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}
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last_iteration =
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(remaining_payload_size == current_payload_size);
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stop_bit = last_iteration ? initial_stop_bit : false;
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/* write slave device address */
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if (first_iteration)
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hw_engine->funcs->write_address(hw_engine, address);
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/* write current portion of data, if requested */
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if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
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hw_engine->funcs->write_data(
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hw_engine,
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current_payload,
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current_payload_size);
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/* execute transaction */
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attributes.start_bit = first_iteration;
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attributes.stop_bit = stop_bit;
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attributes.last_read = last_iteration;
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attributes.transaction_size = current_transaction_size;
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hw_engine->funcs->execute_transaction(hw_engine, &attributes);
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/* wait until transaction is processed; if it fails - quit */
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operation_result = base->funcs->wait_on_operation_result(
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base,
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base->funcs->get_transaction_timeout(
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base, current_transaction_size),
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I2C_CHANNEL_OPERATION_ENGINE_BUSY);
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if (operation_result != I2C_CHANNEL_OPERATION_SUCCEEDED)
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break;
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/* read current portion of data, if requested */
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/* the read offset should be 1 for first sub-transaction,
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* and 0 for any next one */
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if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
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hw_engine->funcs->read_data(hw_engine, current_payload,
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current_payload_size, first_iteration ? 1 : 0);
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/* update loop variables */
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first_iteration = false;
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current_payload += current_payload_size;
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remaining_payload_size -= current_payload_size;
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}
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/* update transaction status */
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switch (operation_result) {
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case I2C_CHANNEL_OPERATION_SUCCEEDED:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
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result = true;
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break;
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case I2C_CHANNEL_OPERATION_NO_RESPONSE:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
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break;
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case I2C_CHANNEL_OPERATION_TIMEOUT:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
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break;
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case I2C_CHANNEL_OPERATION_FAILED:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
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break;
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default:
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i2caux_request->status =
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I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
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}
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return result;
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}
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/*
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* @brief
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* Returns number of microseconds to wait until timeout to be considered
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*/
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uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout(
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const struct i2c_hw_engine *engine,
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uint32_t length)
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{
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const struct i2c_engine *base = &engine->base;
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uint32_t speed = base->funcs->get_speed(base);
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if (!speed)
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return 0;
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/* total timeout = period_timeout * (start + data bits count + stop) */
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return ((1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed) *
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(1 + (length << 3) + 1);
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}
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void dal_i2c_generic_hw_engine_construct(
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struct i2c_generic_hw_engine *engine,
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struct dc_context *ctx)
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{
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dal_i2c_hw_engine_construct(&engine->base, ctx);
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}
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void dal_i2c_generic_hw_engine_destruct(
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struct i2c_generic_hw_engine *engine)
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{
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dal_i2c_hw_engine_destruct(&engine->base);
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}
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