/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/i2caux_interface.h"
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#include "../engine.h"
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#include "../i2c_engine.h"
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#include "../i2c_hw_engine.h"
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#include "../i2c_generic_hw_engine.h"
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/*
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* Header of this unit
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*/
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#include "i2c_hw_engine_dce80.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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#include "dce/dce_8_0_d.h"
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#include "dce/dce_8_0_sh_mask.h"
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/*
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* This unit
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*/
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enum dc_i2c_status {
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DC_I2C_STATUS__DC_I2C_STATUS_IDLE,
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DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW,
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DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW
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};
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enum dc_i2c_arbitration {
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DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
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DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH
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};
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enum {
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/* No timeout in HW
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* (timeout implemented in SW by querying status) */
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I2C_SETUP_TIME_LIMIT = 255,
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I2C_HW_BUFFER_SIZE = 144
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};
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/*
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* @brief
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* Cast 'struct i2c_hw_engine *'
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* to 'struct i2c_hw_engine_dce80 *'
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*/
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#define FROM_I2C_HW_ENGINE(ptr) \
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container_of((ptr), struct i2c_hw_engine_dce80, base)
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/*
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* @brief
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* Cast pointer to 'struct i2c_engine *'
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* to pointer to 'struct i2c_hw_engine_dce80 *'
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*/
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#define FROM_I2C_ENGINE(ptr) \
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FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base))
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/*
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* @brief
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* Cast pointer to 'struct engine *'
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* to 'pointer to struct i2c_hw_engine_dce80 *'
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*/
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#define FROM_ENGINE(ptr) \
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FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
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static void disable_i2c_hw_engine(
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struct i2c_hw_engine_dce80 *engine)
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{
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const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
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uint32_t value = 0;
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struct dc_context *ctx = NULL;
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ctx = engine->base.base.base.ctx;
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value = dm_read_reg(ctx, addr);
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set_reg_field_value(
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value,
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0,
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DC_I2C_DDC1_SETUP,
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DC_I2C_DDC1_ENABLE);
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dm_write_reg(ctx, addr, value);
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}
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static void release_engine(
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struct engine *engine)
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{
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struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
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struct i2c_engine *base = NULL;
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bool safe_to_reset;
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uint32_t value = 0;
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base = &hw_engine->base.base;
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/* Restore original HW engine speed */
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base->funcs->set_speed(base, hw_engine->base.original_speed);
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/* Release I2C */
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{
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value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
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set_reg_field_value(
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value,
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1,
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DC_I2C_ARBITRATION,
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DC_I2C_SW_DONE_USING_I2C_REG);
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dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
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}
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/* Reset HW engine */
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{
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uint32_t i2c_sw_status = 0;
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value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
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i2c_sw_status = get_reg_field_value(
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value,
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DC_I2C_SW_STATUS,
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DC_I2C_SW_STATUS);
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/* if used by SW, safe to reset */
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safe_to_reset = (i2c_sw_status == 1);
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}
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{
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value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
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if (safe_to_reset)
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set_reg_field_value(
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value,
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1,
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DC_I2C_CONTROL,
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DC_I2C_SOFT_RESET);
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set_reg_field_value(
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value,
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1,
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DC_I2C_CONTROL,
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DC_I2C_SW_STATUS_RESET);
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dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
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}
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/* HW I2c engine - clock gating feature */
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if (!hw_engine->engine_keep_power_up_count)
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disable_i2c_hw_engine(hw_engine);
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}
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static void destruct(
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struct i2c_hw_engine_dce80 *engine)
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{
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dal_i2c_hw_engine_destruct(&engine->base);
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}
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static void destroy(
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struct i2c_engine **i2c_engine)
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{
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struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
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destruct(engine);
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kfree(engine);
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*i2c_engine = NULL;
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}
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static bool setup_engine(
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struct i2c_engine *i2c_engine)
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{
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uint32_t value = 0;
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struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
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/* Program pin select */
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{
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const uint32_t addr = mmDC_I2C_CONTROL;
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value = dm_read_reg(i2c_engine->base.ctx, addr);
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set_reg_field_value(
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value,
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0,
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DC_I2C_CONTROL,
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DC_I2C_GO);
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set_reg_field_value(
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value,
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0,
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DC_I2C_CONTROL,
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DC_I2C_SOFT_RESET);
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set_reg_field_value(
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value,
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0,
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DC_I2C_CONTROL,
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DC_I2C_SEND_RESET);
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set_reg_field_value(
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value,
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0,
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DC_I2C_CONTROL,
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DC_I2C_SW_STATUS_RESET);
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set_reg_field_value(
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value,
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0,
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DC_I2C_CONTROL,
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DC_I2C_TRANSACTION_COUNT);
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set_reg_field_value(
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value,
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engine->engine_id,
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DC_I2C_CONTROL,
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DC_I2C_DDC_SELECT);
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dm_write_reg(i2c_engine->base.ctx, addr, value);
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}
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/* Program time limit */
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{
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const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
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value = dm_read_reg(i2c_engine->base.ctx, addr);
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set_reg_field_value(
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value,
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I2C_SETUP_TIME_LIMIT,
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DC_I2C_DDC1_SETUP,
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DC_I2C_DDC1_TIME_LIMIT);
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set_reg_field_value(
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value,
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1,
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DC_I2C_DDC1_SETUP,
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DC_I2C_DDC1_ENABLE);
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dm_write_reg(i2c_engine->base.ctx, addr, value);
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}
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/* Program HW priority
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* set to High - interrupt software I2C at any time
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* Enable restart of SW I2C that was interrupted by HW
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* disable queuing of software while I2C is in use by HW */
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{
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value = dm_read_reg(i2c_engine->base.ctx,
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mmDC_I2C_ARBITRATION);
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set_reg_field_value(
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value,
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0,
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DC_I2C_ARBITRATION,
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DC_I2C_NO_QUEUED_SW_GO);
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set_reg_field_value(
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value,
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DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL,
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DC_I2C_ARBITRATION,
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DC_I2C_SW_PRIORITY);
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dm_write_reg(i2c_engine->base.ctx,
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mmDC_I2C_ARBITRATION, value);
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}
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return true;
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}
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static uint32_t get_speed(
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const struct i2c_engine *i2c_engine)
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{
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const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
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const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
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uint32_t pre_scale = 0;
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uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
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pre_scale = get_reg_field_value(
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value,
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DC_I2C_DDC1_SPEED,
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DC_I2C_DDC1_PRESCALE);
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/* [anaumov] it seems following is unnecessary */
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/*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/
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return pre_scale ?
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engine->reference_frequency / pre_scale :
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engine->base.default_speed;
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}
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static void set_speed(
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struct i2c_engine *i2c_engine,
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uint32_t speed)
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{
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struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
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if (speed) {
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const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
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uint32_t value = dm_read_reg(i2c_engine->base.ctx, addr);
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set_reg_field_value(
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value,
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engine->reference_frequency / speed,
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DC_I2C_DDC1_SPEED,
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DC_I2C_DDC1_PRESCALE);
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set_reg_field_value(
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value,
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2,
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DC_I2C_DDC1_SPEED,
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DC_I2C_DDC1_THRESHOLD);
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dm_write_reg(i2c_engine->base.ctx, addr, value);
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}
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}
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static inline void reset_hw_engine(struct engine *engine)
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{
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uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
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set_reg_field_value(
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value,
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1,
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DC_I2C_CONTROL,
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DC_I2C_SOFT_RESET);
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set_reg_field_value(
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value,
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1,
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DC_I2C_CONTROL,
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DC_I2C_SW_STATUS_RESET);
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dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
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}
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static bool is_hw_busy(struct engine *engine)
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{
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uint32_t i2c_sw_status = 0;
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uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
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i2c_sw_status = get_reg_field_value(
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value,
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DC_I2C_SW_STATUS,
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DC_I2C_SW_STATUS);
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if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
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return false;
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reset_hw_engine(engine);
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value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
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i2c_sw_status = get_reg_field_value(
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value,
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DC_I2C_SW_STATUS,
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DC_I2C_SW_STATUS);
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return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
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}
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/*
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* @brief
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* DC_GPIO_DDC MM register offsets
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*/
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static const uint32_t transaction_addr[] = {
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mmDC_I2C_TRANSACTION0,
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mmDC_I2C_TRANSACTION1,
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mmDC_I2C_TRANSACTION2,
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mmDC_I2C_TRANSACTION3
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};
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static bool process_transaction(
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struct i2c_hw_engine_dce80 *engine,
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struct i2c_request_transaction_data *request)
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{
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uint32_t length = request->length;
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uint8_t *buffer = request->data;
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bool last_transaction = false;
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uint32_t value = 0;
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struct dc_context *ctx = NULL;
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ctx = engine->base.base.base.ctx;
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{
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const uint32_t addr =
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transaction_addr[engine->transaction_count];
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value = dm_read_reg(ctx, addr);
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set_reg_field_value(
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value,
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1,
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DC_I2C_TRANSACTION0,
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DC_I2C_STOP_ON_NACK0);
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set_reg_field_value(
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value,
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1,
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DC_I2C_TRANSACTION0,
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DC_I2C_START0);
|
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if ((engine->transaction_count == 3) ||
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(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
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set_reg_field_value(
|
value,
|
1,
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DC_I2C_TRANSACTION0,
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DC_I2C_STOP0);
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last_transaction = true;
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} else
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set_reg_field_value(
|
value,
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0,
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DC_I2C_TRANSACTION0,
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DC_I2C_STOP0);
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set_reg_field_value(
|
value,
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(0 != (request->action &
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I2CAUX_TRANSACTION_ACTION_I2C_READ)),
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DC_I2C_TRANSACTION0,
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DC_I2C_RW0);
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set_reg_field_value(
|
value,
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length,
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DC_I2C_TRANSACTION0,
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DC_I2C_COUNT0);
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dm_write_reg(ctx, addr, value);
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}
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/* Write the I2C address and I2C data
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* into the hardware circular buffer, one byte per entry.
|
* As an example, the 7-bit I2C slave address for CRT monitor
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* for reading DDC/EDID information is 0b1010001.
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* For an I2C send operation, the LSB must be programmed to 0;
|
* for I2C receive operation, the LSB must be programmed to 1. */
|
|
{
|
value = 0;
|
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set_reg_field_value(
|
value,
|
false,
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DC_I2C_DATA,
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DC_I2C_DATA_RW);
|
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set_reg_field_value(
|
value,
|
request->address,
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DC_I2C_DATA,
|
DC_I2C_DATA);
|
|
if (engine->transaction_count == 0) {
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set_reg_field_value(
|
value,
|
0,
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DC_I2C_DATA,
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DC_I2C_INDEX);
|
|
/*enable index write*/
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set_reg_field_value(
|
value,
|
1,
|
DC_I2C_DATA,
|
DC_I2C_INDEX_WRITE);
|
}
|
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dm_write_reg(ctx, mmDC_I2C_DATA, value);
|
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if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) {
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DATA,
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DC_I2C_INDEX_WRITE);
|
|
while (length) {
|
|
set_reg_field_value(
|
value,
|
*buffer++,
|
DC_I2C_DATA,
|
DC_I2C_DATA);
|
|
dm_write_reg(ctx, mmDC_I2C_DATA, value);
|
--length;
|
}
|
}
|
}
|
|
++engine->transaction_count;
|
engine->buffer_used_bytes += length + 1;
|
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return last_transaction;
|
}
|
|
static void execute_transaction(
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struct i2c_hw_engine_dce80 *engine)
|
{
|
uint32_t value = 0;
|
struct dc_context *ctx = NULL;
|
|
ctx = engine->base.base.base.ctx;
|
|
{
|
const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
|
|
value = dm_read_reg(ctx, addr);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DDC1_SETUP,
|
DC_I2C_DDC1_DATA_DRIVE_EN);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DDC1_SETUP,
|
DC_I2C_DDC1_CLK_DRIVE_EN);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DDC1_SETUP,
|
DC_I2C_DDC1_DATA_DRIVE_SEL);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DDC1_SETUP,
|
DC_I2C_DDC1_INTRA_TRANSACTION_DELAY);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_DDC1_SETUP,
|
DC_I2C_DDC1_INTRA_BYTE_DELAY);
|
|
dm_write_reg(ctx, addr, value);
|
}
|
|
{
|
const uint32_t addr = mmDC_I2C_CONTROL;
|
|
value = dm_read_reg(ctx, addr);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_CONTROL,
|
DC_I2C_SOFT_RESET);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_CONTROL,
|
DC_I2C_SW_STATUS_RESET);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_CONTROL,
|
DC_I2C_SEND_RESET);
|
|
set_reg_field_value(
|
value,
|
0,
|
DC_I2C_CONTROL,
|
DC_I2C_GO);
|
|
set_reg_field_value(
|
value,
|
engine->transaction_count - 1,
|
DC_I2C_CONTROL,
|
DC_I2C_TRANSACTION_COUNT);
|
|
dm_write_reg(ctx, addr, value);
|
}
|
|
/* start I2C transfer */
|
{
|
const uint32_t addr = mmDC_I2C_CONTROL;
|
|
value = dm_read_reg(ctx, addr);
|
|
set_reg_field_value(
|
value,
|
1,
|
DC_I2C_CONTROL,
|
DC_I2C_GO);
|
|
dm_write_reg(ctx, addr, value);
|
}
|
|
/* all transactions were executed and HW buffer became empty
|
* (even though it actually happens when status becomes DONE) */
|
engine->transaction_count = 0;
|
engine->buffer_used_bytes = 0;
|
}
|
|
static void submit_channel_request(
|
struct i2c_engine *engine,
|
struct i2c_request_transaction_data *request)
|
{
|
request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
|
|
if (!process_transaction(FROM_I2C_ENGINE(engine), request))
|
return;
|
|
if (is_hw_busy(&engine->base)) {
|
request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
|
return;
|
}
|
|
execute_transaction(FROM_I2C_ENGINE(engine));
|
}
|
|
static void process_channel_reply(
|
struct i2c_engine *engine,
|
struct i2c_reply_transaction_data *reply)
|
{
|
uint32_t length = reply->length;
|
uint8_t *buffer = reply->data;
|
|
uint32_t value = 0;
|
|
/*set index*/
|
set_reg_field_value(
|
value,
|
length - 1,
|
DC_I2C_DATA,
|
DC_I2C_INDEX);
|
|
set_reg_field_value(
|
value,
|
1,
|
DC_I2C_DATA,
|
DC_I2C_DATA_RW);
|
|
set_reg_field_value(
|
value,
|
1,
|
DC_I2C_DATA,
|
DC_I2C_INDEX_WRITE);
|
|
dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
|
|
while (length) {
|
/* after reading the status,
|
* if the I2C operation executed successfully
|
* (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
|
* should read data bytes from I2C circular data buffer */
|
|
value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
|
|
*buffer++ = get_reg_field_value(
|
value,
|
DC_I2C_DATA,
|
DC_I2C_DATA);
|
|
--length;
|
}
|
}
|
|
static enum i2c_channel_operation_result get_channel_status(
|
struct i2c_engine *engine,
|
uint8_t *returned_bytes)
|
{
|
uint32_t i2c_sw_status = 0;
|
uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
|
|
i2c_sw_status = get_reg_field_value(
|
value,
|
DC_I2C_SW_STATUS,
|
DC_I2C_SW_STATUS);
|
|
if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
|
return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
|
else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK)
|
return I2C_CHANNEL_OPERATION_NO_RESPONSE;
|
else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK)
|
return I2C_CHANNEL_OPERATION_TIMEOUT;
|
else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK)
|
return I2C_CHANNEL_OPERATION_FAILED;
|
else if (value & DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK)
|
return I2C_CHANNEL_OPERATION_SUCCEEDED;
|
|
/*
|
* this is the case when HW used for communication, I2C_SW_STATUS
|
* could be zero
|
*/
|
return I2C_CHANNEL_OPERATION_SUCCEEDED;
|
}
|
|
static uint32_t get_hw_buffer_available_size(
|
const struct i2c_hw_engine *engine)
|
{
|
return I2C_HW_BUFFER_SIZE -
|
FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
|
}
|
|
static uint32_t get_transaction_timeout(
|
const struct i2c_hw_engine *engine,
|
uint32_t length)
|
{
|
uint32_t speed = engine->base.funcs->get_speed(&engine->base);
|
|
uint32_t period_timeout;
|
uint32_t num_of_clock_stretches;
|
|
if (!speed)
|
return 0;
|
|
period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
|
|
num_of_clock_stretches = 1 + (length << 3) + 1;
|
num_of_clock_stretches +=
|
(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
|
(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
|
|
return period_timeout * num_of_clock_stretches;
|
}
|
|
/*
|
* @brief
|
* DC_I2C_DDC1_SETUP MM register offsets
|
*
|
* @note
|
* The indices of this offset array are DDC engine IDs
|
*/
|
static const int32_t ddc_setup_offset[] = {
|
|
mmDC_I2C_DDC1_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 1 */
|
mmDC_I2C_DDC2_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 2 */
|
mmDC_I2C_DDC3_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 3 */
|
mmDC_I2C_DDC4_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 4 */
|
mmDC_I2C_DDC5_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 5 */
|
mmDC_I2C_DDC6_SETUP - mmDC_I2C_DDC1_SETUP, /* DDC Engine 6 */
|
mmDC_I2C_DDCVGA_SETUP - mmDC_I2C_DDC1_SETUP /* DDC Engine 7 */
|
};
|
|
/*
|
* @brief
|
* DC_I2C_DDC1_SPEED MM register offsets
|
*
|
* @note
|
* The indices of this offset array are DDC engine IDs
|
*/
|
static const int32_t ddc_speed_offset[] = {
|
mmDC_I2C_DDC1_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 1 */
|
mmDC_I2C_DDC2_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 2 */
|
mmDC_I2C_DDC3_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 3 */
|
mmDC_I2C_DDC4_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 4 */
|
mmDC_I2C_DDC5_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 5 */
|
mmDC_I2C_DDC6_SPEED - mmDC_I2C_DDC1_SPEED, /* DDC Engine 6 */
|
mmDC_I2C_DDCVGA_SPEED - mmDC_I2C_DDC1_SPEED /* DDC Engine 7 */
|
};
|
|
static const struct i2c_engine_funcs i2c_engine_funcs = {
|
.destroy = destroy,
|
.get_speed = get_speed,
|
.set_speed = set_speed,
|
.setup_engine = setup_engine,
|
.submit_channel_request = submit_channel_request,
|
.process_channel_reply = process_channel_reply,
|
.get_channel_status = get_channel_status,
|
.acquire_engine = dal_i2c_hw_engine_acquire_engine,
|
};
|
|
static const struct engine_funcs engine_funcs = {
|
.release_engine = release_engine,
|
.get_engine_type = dal_i2c_hw_engine_get_engine_type,
|
.acquire = dal_i2c_engine_acquire,
|
.submit_request = dal_i2c_hw_engine_submit_request,
|
};
|
|
static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = {
|
.get_hw_buffer_available_size =
|
get_hw_buffer_available_size,
|
.get_transaction_timeout =
|
get_transaction_timeout,
|
.wait_on_operation_result =
|
dal_i2c_hw_engine_wait_on_operation_result,
|
};
|
|
static void construct(
|
struct i2c_hw_engine_dce80 *engine,
|
const struct i2c_hw_engine_dce80_create_arg *arg)
|
{
|
dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
|
|
engine->base.base.base.funcs = &engine_funcs;
|
engine->base.base.funcs = &i2c_engine_funcs;
|
engine->base.funcs = &i2c_hw_engine_funcs;
|
engine->base.default_speed = arg->default_speed;
|
engine->addr.DC_I2C_DDCX_SETUP =
|
mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
|
engine->addr.DC_I2C_DDCX_SPEED =
|
mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];
|
|
engine->engine_id = arg->engine_id;
|
engine->reference_frequency = arg->reference_frequency;
|
engine->buffer_used_bytes = 0;
|
engine->transaction_count = 0;
|
engine->engine_keep_power_up_count = 1;
|
}
|
|
struct i2c_engine *dal_i2c_hw_engine_dce80_create(
|
const struct i2c_hw_engine_dce80_create_arg *arg)
|
{
|
struct i2c_hw_engine_dce80 *engine;
|
|
if (!arg) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
if ((arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t)) ||
|
(arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t)) ||
|
!arg->reference_frequency) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL);
|
|
if (!engine) {
|
BREAK_TO_DEBUGGER();
|
return NULL;
|
}
|
|
construct(engine, arg);
|
return &engine->base.base;
|
}
|
