/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/i2caux_interface.h"
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#include "../i2caux.h"
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#include "../engine.h"
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#include "../i2c_engine.h"
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#include "../i2c_sw_engine.h"
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#include "../i2c_hw_engine.h"
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/*
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* Header of this unit
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*/
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#include "i2caux_dce110.h"
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#include "i2c_sw_engine_dce110.h"
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#include "i2c_hw_engine_dce110.h"
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#include "aux_engine_dce110.h"
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#include "../../dc.h"
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#include "dc_types.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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/*
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* This unit
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*/
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/*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
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#define FROM_I2C_AUX(ptr) \
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container_of((ptr), struct i2caux_dce110, base)
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static void destruct(
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struct i2caux_dce110 *i2caux_dce110)
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{
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dal_i2caux_destruct(&i2caux_dce110->base);
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}
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static void destroy(
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struct i2caux **i2c_engine)
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{
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struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
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destruct(i2caux_dce110);
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kfree(i2caux_dce110);
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*i2c_engine = NULL;
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}
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static struct i2c_engine *acquire_i2c_hw_engine(
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struct i2caux *i2caux,
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struct ddc *ddc)
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{
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struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
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struct i2c_engine *engine = NULL;
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/* generic hw engine is not used for EDID read
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* It may be needed for external i2c device, like thermal chip,
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* TODO will be implemented when needed.
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* check dce80 bool non_generic for generic hw engine;
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*/
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if (!ddc)
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return NULL;
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if (ddc->hw_info.hw_supported) {
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enum gpio_ddc_line line = dal_ddc_get_line(ddc);
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if (line < GPIO_DDC_LINE_COUNT)
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engine = i2caux->i2c_hw_engines[line];
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}
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if (!engine)
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return NULL;
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if (!i2caux_dce110->i2c_hw_buffer_in_use &&
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engine->base.funcs->acquire(&engine->base, ddc)) {
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i2caux_dce110->i2c_hw_buffer_in_use = true;
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return engine;
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}
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return NULL;
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}
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static void release_engine(
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struct i2caux *i2caux,
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struct engine *engine)
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{
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struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
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if (engine->funcs->get_engine_type(engine) ==
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I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
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i2caux_dce110->i2c_hw_buffer_in_use = false;
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dal_i2caux_release_engine(i2caux, engine);
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}
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static const enum gpio_ddc_line hw_ddc_lines[] = {
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GPIO_DDC_LINE_DDC1,
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GPIO_DDC_LINE_DDC2,
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GPIO_DDC_LINE_DDC3,
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GPIO_DDC_LINE_DDC4,
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GPIO_DDC_LINE_DDC5,
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GPIO_DDC_LINE_DDC6,
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};
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static const enum gpio_ddc_line hw_aux_lines[] = {
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GPIO_DDC_LINE_DDC1,
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GPIO_DDC_LINE_DDC2,
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GPIO_DDC_LINE_DDC3,
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GPIO_DDC_LINE_DDC4,
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GPIO_DDC_LINE_DDC5,
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GPIO_DDC_LINE_DDC6,
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};
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/* function table */
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static const struct i2caux_funcs i2caux_funcs = {
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.destroy = destroy,
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.acquire_i2c_hw_engine = acquire_i2c_hw_engine,
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.release_engine = release_engine,
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.acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
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.acquire_aux_engine = dal_i2caux_acquire_aux_engine,
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};
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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/* set register offset */
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#define SR(reg_name)\
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.reg_name = mm ## reg_name
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/* set register offset with instance */
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#define SRI(reg_name, block, id)\
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.reg_name = mm ## block ## id ## _ ## reg_name
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#define aux_regs(id)\
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[id] = {\
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AUX_COMMON_REG_LIST(id), \
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.AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
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}
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#define hw_engine_regs(id)\
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{\
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I2C_HW_ENGINE_COMMON_REG_LIST(id) \
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}
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static const struct dce110_aux_registers dce110_aux_regs[] = {
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aux_regs(0),
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aux_regs(1),
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aux_regs(2),
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aux_regs(3),
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aux_regs(4),
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aux_regs(5)
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};
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static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
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hw_engine_regs(1),
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hw_engine_regs(2),
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hw_engine_regs(3),
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hw_engine_regs(4),
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hw_engine_regs(5),
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hw_engine_regs(6)
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};
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static const struct dce110_i2c_hw_engine_shift i2c_shift = {
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I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
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};
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static const struct dce110_i2c_hw_engine_mask i2c_mask = {
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I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
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};
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void dal_i2caux_dce110_construct(
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struct i2caux_dce110 *i2caux_dce110,
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struct dc_context *ctx,
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unsigned int num_i2caux_inst,
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const struct dce110_aux_registers aux_regs[],
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const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
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const struct dce110_i2c_hw_engine_shift *i2c_shift,
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const struct dce110_i2c_hw_engine_mask *i2c_mask)
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{
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uint32_t i = 0;
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uint32_t reference_frequency = 0;
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bool use_i2c_sw_engine = false;
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struct i2caux *base = NULL;
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/*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
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* does not return 48KHz, we need hard coded for 48Khz.
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* Some BIOS setting incorrect cause this
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* For production, we always get value from BIOS*/
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reference_frequency =
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dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
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base = &i2caux_dce110->base;
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dal_i2caux_construct(base, ctx);
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i2caux_dce110->base.funcs = &i2caux_funcs;
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i2caux_dce110->i2c_hw_buffer_in_use = false;
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/* Create I2C engines (DDC lines per connector)
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* different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
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*/
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do {
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enum gpio_ddc_line line_id = hw_ddc_lines[i];
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struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
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if (use_i2c_sw_engine) {
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struct i2c_sw_engine_dce110_create_arg sw_arg;
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sw_arg.engine_id = i;
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sw_arg.default_speed = base->default_i2c_sw_speed;
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sw_arg.ctx = ctx;
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base->i2c_sw_engines[line_id] =
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dal_i2c_sw_engine_dce110_create(&sw_arg);
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}
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hw_arg_dce110.engine_id = i;
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hw_arg_dce110.reference_frequency = reference_frequency;
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hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
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hw_arg_dce110.ctx = ctx;
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hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
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hw_arg_dce110.i2c_shift = i2c_shift;
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hw_arg_dce110.i2c_mask = i2c_mask;
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base->i2c_hw_engines[line_id] =
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dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
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if (base->i2c_hw_engines[line_id] != NULL) {
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switch (ctx->dce_version) {
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case DCN_VERSION_1_0:
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base->i2c_hw_engines[line_id]->setup_limit =
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I2C_SETUP_TIME_LIMIT_DCN;
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base->i2c_hw_engines[line_id]->send_reset_length = 0;
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break;
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default:
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base->i2c_hw_engines[line_id]->setup_limit =
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I2C_SETUP_TIME_LIMIT_DCE;
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base->i2c_hw_engines[line_id]->send_reset_length = 0;
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break;
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}
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}
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++i;
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} while (i < num_i2caux_inst);
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/* Create AUX engines for all lines which has assisted HW AUX
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* 'i' (loop counter) used as DDC/AUX engine_id */
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i = 0;
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do {
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enum gpio_ddc_line line_id = hw_aux_lines[i];
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struct aux_engine_dce110_init_data aux_init_data;
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aux_init_data.engine_id = i;
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aux_init_data.timeout_period = base->aux_timeout_period;
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aux_init_data.ctx = ctx;
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aux_init_data.regs = &aux_regs[i];
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base->aux_engines[line_id] =
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dal_aux_engine_dce110_create(&aux_init_data);
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++i;
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} while (i < num_i2caux_inst);
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/*TODO Generic I2C SW and HW*/
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}
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/*
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* dal_i2caux_dce110_create
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*
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* @brief
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* public interface to allocate memory for DCE11 I2CAUX
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*
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* @param
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* struct adapter_service *as - [in]
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* struct dc_context *ctx - [in]
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*
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* @return
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* pointer to the base struct of DCE11 I2CAUX
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*/
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struct i2caux *dal_i2caux_dce110_create(
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struct dc_context *ctx)
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{
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struct i2caux_dce110 *i2caux_dce110 =
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kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
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if (!i2caux_dce110) {
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ASSERT_CRITICAL(false);
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return NULL;
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}
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dal_i2caux_dce110_construct(i2caux_dce110,
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ctx,
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ARRAY_SIZE(dce110_aux_regs),
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dce110_aux_regs,
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i2c_hw_engine_regs,
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&i2c_shift,
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&i2c_mask);
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return &i2caux_dce110->base;
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}
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