/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/*
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* Pre-requisites: headers required by header of this unit
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*/
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#include "include/i2caux_interface.h"
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#include "../engine.h"
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#include "../aux_engine.h"
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/*
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* Header of this unit
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*/
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#include "aux_engine_dce110.h"
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/*
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* Post-requisites: headers required by this unit
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*/
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#include "dce/dce_11_0_sh_mask.h"
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#define CTX \
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aux110->base.base.ctx
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#define REG(reg_name)\
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(aux110->regs->reg_name)
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#include "reg_helper.h"
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/*
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* This unit
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*/
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/*
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* @brief
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* Cast 'struct aux_engine *'
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* to 'struct aux_engine_dce110 *'
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*/
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#define FROM_AUX_ENGINE(ptr) \
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container_of((ptr), struct aux_engine_dce110, base)
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/*
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* @brief
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* Cast 'struct engine *'
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* to 'struct aux_engine_dce110 *'
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*/
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#define FROM_ENGINE(ptr) \
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FROM_AUX_ENGINE(container_of((ptr), struct aux_engine, base))
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static void release_engine(
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struct engine *engine)
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{
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struct aux_engine_dce110 *aux110 = FROM_ENGINE(engine);
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REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, 1);
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}
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static void destruct(
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struct aux_engine_dce110 *engine);
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static void destroy(
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struct aux_engine **aux_engine)
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{
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struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
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destruct(engine);
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kfree(engine);
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*aux_engine = NULL;
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}
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#define SW_CAN_ACCESS_AUX 1
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#define DMCU_CAN_ACCESS_AUX 2
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static bool is_engine_available(
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struct aux_engine *engine)
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{
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struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
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uint32_t value = REG_READ(AUX_ARB_CONTROL);
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uint32_t field = get_reg_field_value(
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value,
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AUX_ARB_CONTROL,
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AUX_REG_RW_CNTL_STATUS);
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return (field != DMCU_CAN_ACCESS_AUX);
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}
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static bool acquire_engine(
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struct aux_engine *engine)
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{
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struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
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uint32_t value = REG_READ(AUX_ARB_CONTROL);
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uint32_t field = get_reg_field_value(
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value,
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AUX_ARB_CONTROL,
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AUX_REG_RW_CNTL_STATUS);
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if (field == DMCU_CAN_ACCESS_AUX)
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return false;
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/* enable AUX before request SW to access AUX */
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value = REG_READ(AUX_CONTROL);
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field = get_reg_field_value(value,
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AUX_CONTROL,
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AUX_EN);
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if (field == 0) {
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set_reg_field_value(
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value,
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1,
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AUX_CONTROL,
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AUX_EN);
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if (REG(AUX_RESET_MASK)) {
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/*DP_AUX block as part of the enable sequence*/
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set_reg_field_value(
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value,
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1,
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AUX_CONTROL,
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AUX_RESET);
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}
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REG_WRITE(AUX_CONTROL, value);
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if (REG(AUX_RESET_MASK)) {
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/*poll HW to make sure reset it done*/
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REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1,
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1, 11);
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set_reg_field_value(
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value,
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0,
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AUX_CONTROL,
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AUX_RESET);
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REG_WRITE(AUX_CONTROL, value);
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REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0,
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1, 11);
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}
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} /*if (field)*/
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/* request SW to access AUX */
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REG_UPDATE(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, 1);
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value = REG_READ(AUX_ARB_CONTROL);
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field = get_reg_field_value(
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value,
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AUX_ARB_CONTROL,
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AUX_REG_RW_CNTL_STATUS);
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return (field == SW_CAN_ACCESS_AUX);
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}
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#define COMPOSE_AUX_SW_DATA_16_20(command, address) \
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((command) | ((0xF0000 & (address)) >> 16))
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#define COMPOSE_AUX_SW_DATA_8_15(address) \
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((0xFF00 & (address)) >> 8)
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#define COMPOSE_AUX_SW_DATA_0_7(address) \
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(0xFF & (address))
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static void submit_channel_request(
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struct aux_engine *engine,
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struct aux_request_transaction_data *request)
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{
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struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
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uint32_t value;
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uint32_t length;
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bool is_write =
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((request->type == AUX_TRANSACTION_TYPE_DP) &&
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(request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) ||
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((request->type == AUX_TRANSACTION_TYPE_I2C) &&
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((request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT)));
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if (REG(AUXN_IMPCAL)) {
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/* clear_aux_error */
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REG_UPDATE_SEQ(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK,
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1,
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0);
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK,
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1,
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0);
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/* force_default_calibrate */
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REG_UPDATE_1BY1_2(AUXN_IMPCAL,
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AUXN_IMPCAL_ENABLE, 1,
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AUXN_IMPCAL_OVERRIDE_ENABLE, 0);
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/* bug? why AUXN update EN and OVERRIDE_EN 1 by 1 while AUX P toggles OVERRIDE? */
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REG_UPDATE_SEQ(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE,
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1,
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0);
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}
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/* set the delay and the number of bytes to write */
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/* The length include
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* the 4 bit header and the 20 bit address
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* (that is 3 byte).
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* If the requested length is non zero this means
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* an addition byte specifying the length is required. */
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length = request->length ? 4 : 3;
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if (is_write)
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length += request->length;
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REG_UPDATE_2(AUX_SW_CONTROL,
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AUX_SW_START_DELAY, request->delay,
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AUX_SW_WR_BYTES, length);
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/* program action and address and payload data (if 'is_write') */
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value = REG_UPDATE_4(AUX_SW_DATA,
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AUX_SW_INDEX, 0,
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AUX_SW_DATA_RW, 0,
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AUX_SW_AUTOINCREMENT_DISABLE, 1,
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AUX_SW_DATA, COMPOSE_AUX_SW_DATA_16_20(request->action, request->address));
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value = REG_SET_2(AUX_SW_DATA, value,
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AUX_SW_AUTOINCREMENT_DISABLE, 0,
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AUX_SW_DATA, COMPOSE_AUX_SW_DATA_8_15(request->address));
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value = REG_SET(AUX_SW_DATA, value,
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AUX_SW_DATA, COMPOSE_AUX_SW_DATA_0_7(request->address));
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if (request->length) {
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value = REG_SET(AUX_SW_DATA, value,
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AUX_SW_DATA, request->length - 1);
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}
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if (is_write) {
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/* Load the HW buffer with the Data to be sent.
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* This is relevant for write operation.
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* For read, the data recived data will be
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* processed in process_channel_reply(). */
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uint32_t i = 0;
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while (i < request->length) {
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value = REG_SET(AUX_SW_DATA, value,
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AUX_SW_DATA, request->data[i]);
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++i;
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}
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}
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REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
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REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
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10, aux110->timeout_period/10);
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REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
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}
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static int read_channel_reply(struct aux_engine *engine, uint32_t size,
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uint8_t *buffer, uint8_t *reply_result,
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uint32_t *sw_status)
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{
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struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
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uint32_t bytes_replied;
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uint32_t reply_result_32;
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*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,
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&bytes_replied);
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/* In case HPD is LOW, exit AUX transaction */
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if ((*sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
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return -1;
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/* Need at least the status byte */
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if (!bytes_replied)
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return -1;
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REG_UPDATE_1BY1_3(AUX_SW_DATA,
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AUX_SW_INDEX, 0,
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AUX_SW_AUTOINCREMENT_DISABLE, 1,
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AUX_SW_DATA_RW, 1);
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REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);
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reply_result_32 = reply_result_32 >> 4;
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*reply_result = (uint8_t)reply_result_32;
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if (reply_result_32 == 0) { /* ACK */
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uint32_t i = 0;
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/* First byte was already used to get the command status */
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--bytes_replied;
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/* Do not overflow buffer */
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if (bytes_replied > size)
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return -1;
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while (i < bytes_replied) {
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uint32_t aux_sw_data_val;
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REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
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buffer[i] = aux_sw_data_val;
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++i;
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}
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return i;
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}
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return 0;
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}
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static void process_channel_reply(
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struct aux_engine *engine,
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struct aux_reply_transaction_data *reply)
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{
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int bytes_replied;
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uint8_t reply_result;
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uint32_t sw_status;
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bytes_replied = read_channel_reply(engine, reply->length, reply->data,
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&reply_result, &sw_status);
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/* in case HPD is LOW, exit AUX transaction */
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if ((sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
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reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
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return;
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}
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if (bytes_replied < 0) {
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/* Need to handle an error case...
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* Hopefully, upper layer function won't call this function if
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* the number of bytes in the reply was 0, because there was
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* surely an error that was asserted that should have been
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* handled for hot plug case, this could happens
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*/
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if (!(sw_status & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK)) {
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reply->status = AUX_TRANSACTION_REPLY_INVALID;
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ASSERT_CRITICAL(false);
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return;
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}
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} else {
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switch (reply_result) {
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case 0: /* ACK */
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reply->status = AUX_TRANSACTION_REPLY_AUX_ACK;
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break;
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case 1: /* NACK */
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reply->status = AUX_TRANSACTION_REPLY_AUX_NACK;
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break;
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case 2: /* DEFER */
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reply->status = AUX_TRANSACTION_REPLY_AUX_DEFER;
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break;
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case 4: /* AUX ACK / I2C NACK */
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reply->status = AUX_TRANSACTION_REPLY_I2C_NACK;
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break;
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case 8: /* AUX ACK / I2C DEFER */
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reply->status = AUX_TRANSACTION_REPLY_I2C_DEFER;
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break;
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default:
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reply->status = AUX_TRANSACTION_REPLY_INVALID;
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}
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}
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}
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static enum aux_channel_operation_result get_channel_status(
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struct aux_engine *engine,
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uint8_t *returned_bytes)
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{
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struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
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uint32_t value;
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if (returned_bytes == NULL) {
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/*caller pass NULL pointer*/
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ASSERT_CRITICAL(false);
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return AUX_CHANNEL_OPERATION_FAILED_REASON_UNKNOWN;
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}
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*returned_bytes = 0;
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/* poll to make sure that SW_DONE is asserted */
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value = REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
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10, aux110->timeout_period/10);
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/* in case HPD is LOW, exit AUX transaction */
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if ((value & AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK))
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return AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
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/* Note that the following bits are set in 'status.bits'
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* during CTS 4.2.1.2 (FW 3.3.1):
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* AUX_SW_RX_MIN_COUNT_VIOL, AUX_SW_RX_INVALID_STOP,
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* AUX_SW_RX_RECV_NO_DET, AUX_SW_RX_RECV_INVALID_H.
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*
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* AUX_SW_RX_MIN_COUNT_VIOL is an internal,
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* HW debugging bit and should be ignored. */
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if (value & AUX_SW_STATUS__AUX_SW_DONE_MASK) {
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if ((value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK) ||
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(value & AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK))
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return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
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else if ((value & AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK) ||
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(value & AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK) ||
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(value &
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AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK) ||
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(value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
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return AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
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*returned_bytes = get_reg_field_value(value,
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AUX_SW_STATUS,
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AUX_SW_REPLY_BYTE_COUNT);
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if (*returned_bytes == 0)
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return
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AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY;
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else {
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*returned_bytes -= 1;
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return AUX_CHANNEL_OPERATION_SUCCEEDED;
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}
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} else {
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/*time_elapsed >= aux_engine->timeout_period
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* AUX_SW_STATUS__AUX_SW_HPD_DISCON = at this point
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*/
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ASSERT_CRITICAL(false);
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return AUX_CHANNEL_OPERATION_FAILED_TIMEOUT;
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}
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}
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static const struct aux_engine_funcs aux_engine_funcs = {
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.destroy = destroy,
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.acquire_engine = acquire_engine,
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.submit_channel_request = submit_channel_request,
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.process_channel_reply = process_channel_reply,
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.read_channel_reply = read_channel_reply,
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.get_channel_status = get_channel_status,
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.is_engine_available = is_engine_available,
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};
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static const struct engine_funcs engine_funcs = {
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.release_engine = release_engine,
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.submit_request = dal_aux_engine_submit_request,
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.get_engine_type = dal_aux_engine_get_engine_type,
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.acquire = dal_aux_engine_acquire,
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};
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static void construct(
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struct aux_engine_dce110 *engine,
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const struct aux_engine_dce110_init_data *aux_init_data)
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{
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dal_aux_engine_construct(&engine->base, aux_init_data->ctx);
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engine->base.base.funcs = &engine_funcs;
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engine->base.funcs = &aux_engine_funcs;
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engine->timeout_period = aux_init_data->timeout_period;
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engine->regs = aux_init_data->regs;
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}
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static void destruct(
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struct aux_engine_dce110 *engine)
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{
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dal_aux_engine_destruct(&engine->base);
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}
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struct aux_engine *dal_aux_engine_dce110_create(
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const struct aux_engine_dce110_init_data *aux_init_data)
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{
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struct aux_engine_dce110 *engine;
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if (!aux_init_data) {
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ASSERT_CRITICAL(false);
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return NULL;
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}
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engine = kzalloc(sizeof(*engine), GFP_KERNEL);
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if (!engine) {
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ASSERT_CRITICAL(false);
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return NULL;
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}
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construct(engine, aux_init_data);
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return &engine->base;
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}
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