/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DM_SERVICES_TYPES_H__
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#define __DM_SERVICES_TYPES_H__
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#include "os_types.h"
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#include "dc_types.h"
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struct pp_smu_funcs_rv;
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struct dm_pp_clock_range {
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int min_khz;
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int max_khz;
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};
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enum dm_pp_clocks_state {
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DM_PP_CLOCKS_STATE_INVALID,
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DM_PP_CLOCKS_STATE_ULTRA_LOW,
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DM_PP_CLOCKS_STATE_LOW,
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DM_PP_CLOCKS_STATE_NOMINAL,
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DM_PP_CLOCKS_STATE_PERFORMANCE,
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/* Starting from DCE11, Max 8 levels of DPM state supported. */
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DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_0,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_1,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_2,
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/* to be backward compatible */
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DM_PP_CLOCKS_DPM_STATE_LEVEL_3,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_4,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_5,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_6,
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DM_PP_CLOCKS_DPM_STATE_LEVEL_7,
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DM_PP_CLOCKS_MAX_STATES
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};
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struct dm_pp_gpu_clock_range {
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enum dm_pp_clocks_state clock_state;
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struct dm_pp_clock_range sclk;
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struct dm_pp_clock_range mclk;
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struct dm_pp_clock_range eclk;
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struct dm_pp_clock_range dclk;
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};
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enum dm_pp_clock_type {
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DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1,
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DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */
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DM_PP_CLOCK_TYPE_MEMORY_CLK,
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DM_PP_CLOCK_TYPE_DCFCLK,
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DM_PP_CLOCK_TYPE_DCEFCLK,
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DM_PP_CLOCK_TYPE_SOCCLK,
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DM_PP_CLOCK_TYPE_PIXELCLK,
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DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
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DM_PP_CLOCK_TYPE_DPPCLK,
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DM_PP_CLOCK_TYPE_FCLK,
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};
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#define DC_DECODE_PP_CLOCK_TYPE(clk_type) \
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(clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
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(clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
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(clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : "Invalid"
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#define DM_PP_MAX_CLOCK_LEVELS 8
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struct dm_pp_clock_levels {
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uint32_t num_levels;
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uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS];
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};
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struct dm_pp_clock_with_latency {
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uint32_t clocks_in_khz;
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uint32_t latency_in_us;
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};
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struct dm_pp_clock_levels_with_latency {
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uint32_t num_levels;
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struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS];
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};
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struct dm_pp_clock_with_voltage {
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uint32_t clocks_in_khz;
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uint32_t voltage_in_mv;
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};
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struct dm_pp_clock_levels_with_voltage {
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uint32_t num_levels;
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struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS];
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};
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struct dm_pp_single_disp_config {
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enum signal_type signal;
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uint8_t transmitter;
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uint8_t ddi_channel_mapping;
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uint8_t pipe_idx;
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uint32_t src_height;
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uint32_t src_width;
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uint32_t v_refresh;
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uint32_t sym_clock; /* HDMI only */
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struct dc_link_settings link_settings; /* DP only */
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};
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#define MAX_WM_SETS 4
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enum dm_pp_wm_set_id {
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WM_SET_A = 0,
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WM_SET_B,
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WM_SET_C,
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WM_SET_D,
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WM_SET_INVALID = 0xffff,
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};
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struct dm_pp_clock_range_for_wm_set {
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enum dm_pp_wm_set_id wm_set_id;
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uint32_t wm_min_eng_clk_in_khz;
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uint32_t wm_max_eng_clk_in_khz;
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uint32_t wm_min_mem_clk_in_khz;
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uint32_t wm_max_mem_clk_in_khz;
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};
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struct dm_pp_wm_sets_with_clock_ranges {
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uint32_t num_wm_sets;
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struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS];
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};
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struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
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enum dm_pp_wm_set_id wm_set_id;
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uint32_t wm_min_dcfclk_clk_in_khz;
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uint32_t wm_max_dcfclk_clk_in_khz;
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uint32_t wm_min_mem_clk_in_khz;
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uint32_t wm_max_mem_clk_in_khz;
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};
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struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
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enum dm_pp_wm_set_id wm_set_id;
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uint32_t wm_min_socclk_clk_in_khz;
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uint32_t wm_max_socclk_clk_in_khz;
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uint32_t wm_min_mem_clk_in_khz;
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uint32_t wm_max_mem_clk_in_khz;
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};
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struct dm_pp_wm_sets_with_clock_ranges_soc15 {
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uint32_t num_wm_dmif_sets;
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uint32_t num_wm_mcif_sets;
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struct dm_pp_clock_range_for_dmif_wm_set_soc15
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wm_dmif_clocks_ranges[MAX_WM_SETS];
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struct dm_pp_clock_range_for_mcif_wm_set_soc15
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wm_mcif_clocks_ranges[MAX_WM_SETS];
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};
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#define MAX_DISPLAY_CONFIGS 6
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struct dm_pp_display_configuration {
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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uint32_t min_memory_clock_khz;
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uint32_t min_engine_clock_khz;
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uint32_t min_engine_clock_deep_sleep_khz;
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uint32_t avail_mclk_switch_time_us;
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uint32_t avail_mclk_switch_time_in_disp_active_us;
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uint32_t min_dcfclock_khz;
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uint32_t min_dcfc_deep_sleep_clock_khz;
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uint32_t disp_clk_khz;
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bool all_displays_in_sync;
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uint8_t display_count;
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struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS];
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/*Controller Index of primary display - used in MCLK SMC switching hang
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* SW Workaround*/
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uint8_t crtc_index;
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/*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
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uint32_t line_time_in_us;
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};
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struct dm_bl_data_point {
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/* Brightness level in percentage */
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uint8_t luminance;
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/* Brightness level as effective value in range 0-255,
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* corresponding to above percentage
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*/
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uint8_t signalLevel;
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};
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/* Total size of the structure should not exceed 256 bytes */
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struct dm_acpi_atif_backlight_caps {
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uint16_t size; /* Bytes 0-1 (2 bytes) */
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uint16_t flags; /* Byted 2-3 (2 bytes) */
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uint8_t errorCode; /* Byte 4 */
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uint8_t acLevelPercentage; /* Byte 5 */
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uint8_t dcLevelPercentage; /* Byte 6 */
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uint8_t minInputSignal; /* Byte 7 */
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uint8_t maxInputSignal; /* Byte 8 */
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uint8_t numOfDataPoints; /* Byte 9 */
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struct dm_bl_data_point dataPoints[99]; /* Bytes 10-207 (198 bytes)*/
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};
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enum dm_acpi_display_type {
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AcpiDisplayType_LCD1 = 0,
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AcpiDisplayType_CRT1 = 1,
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AcpiDisplayType_DFP1 = 3,
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AcpiDisplayType_CRT2 = 4,
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AcpiDisplayType_LCD2 = 5,
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AcpiDisplayType_DFP2 = 7,
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AcpiDisplayType_DFP3 = 9,
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AcpiDisplayType_DFP4 = 10,
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AcpiDisplayType_DFP5 = 11,
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AcpiDisplayType_DFP6 = 12
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};
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struct dm_pp_power_level_change_request {
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enum dm_pp_clocks_state power_level;
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};
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struct dm_pp_clock_for_voltage_req {
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enum dm_pp_clock_type clk_type;
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uint32_t clocks_in_khz;
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};
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struct dm_pp_static_clock_info {
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uint32_t max_sclk_khz;
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uint32_t max_mclk_khz;
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/* max possible display block clocks state */
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enum dm_pp_clocks_state max_clocks_state;
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};
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struct dtn_min_clk_info {
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uint32_t disp_clk_khz;
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uint32_t min_engine_clock_khz;
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uint32_t min_memory_clock_khz;
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};
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#endif
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