/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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/* include DCE8 register header files */
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#include "dce/dce_8_0_d.h"
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#include "dce/dce_8_0_sh_mask.h"
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#include "dc_types.h"
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#include "include/grph_object_id.h"
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#include "include/logger_interface.h"
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#include "../dce110/dce110_timing_generator.h"
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#include "dce80_timing_generator.h"
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#include "timing_generator.h"
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enum black_color_format {
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BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, /* used as index in array */
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BLACK_COLOR_FORMAT_RGB_LIMITED,
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BLACK_COLOR_FORMAT_YUV_TV,
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BLACK_COLOR_FORMAT_YUV_CV,
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BLACK_COLOR_FORMAT_YUV_SUPER_AA,
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BLACK_COLOR_FORMAT_COUNT
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};
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static const struct dce110_timing_generator_offsets reg_offsets[] = {
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{
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.crtc = (mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP3_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP4_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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},
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{
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.crtc = (mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL - mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL),
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.dcp = (mmDCP5_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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}
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};
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#define NUMBER_OF_FRAME_TO_WAIT_ON_TRIGGERED_RESET 10
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#define MAX_H_TOTAL (CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1)
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#define MAX_V_TOTAL (CRTC_V_TOTAL__CRTC_V_TOTAL_MASKhw + 1)
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#define CRTC_REG(reg) (reg + tg110->offsets.crtc)
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#define DCP_REG(reg) (reg + tg110->offsets.dcp)
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#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
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static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
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{
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uint64_t pix_dur;
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uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
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+ DCE110TG_FROM_TG(tg)->offsets.dmif;
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uint32_t value = dm_read_reg(tg->ctx, addr);
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if (pix_clk_khz == 0)
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return;
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pix_dur = 1000000000 / pix_clk_khz;
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set_reg_field_value(
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value,
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pix_dur,
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DPG_PIPE_ARBITRATION_CONTROL1,
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PIXEL_DURATION);
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dm_write_reg(tg->ctx, addr, value);
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}
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static void program_timing(struct timing_generator *tg,
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const struct dc_crtc_timing *timing,
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bool use_vbios)
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{
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if (!use_vbios)
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program_pix_dur(tg, timing->pix_clk_khz);
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dce110_tg_program_timing(tg, timing, use_vbios);
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}
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static void dce80_timing_generator_enable_advanced_request(
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struct timing_generator *tg,
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bool enable,
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const struct dc_crtc_timing *timing)
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{
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struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
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uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
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uint32_t value = dm_read_reg(tg->ctx, addr);
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if (enable) {
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set_reg_field_value(
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value,
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0,
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CRTC_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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} else {
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_LEGACY_REQUESTOR_EN);
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}
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if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
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set_reg_field_value(
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value,
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3,
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CRTC_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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set_reg_field_value(
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value,
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0,
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CRTC_START_LINE_CONTROL,
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CRTC_PREFETCH_EN);
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} else {
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set_reg_field_value(
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value,
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4,
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CRTC_START_LINE_CONTROL,
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CRTC_ADVANCED_START_LINE_POSITION);
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_PREFETCH_EN);
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}
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_PROGRESSIVE_START_LINE_EARLY);
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set_reg_field_value(
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value,
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1,
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CRTC_START_LINE_CONTROL,
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CRTC_INTERLACE_START_LINE_EARLY);
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dm_write_reg(tg->ctx, addr, value);
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}
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static const struct timing_generator_funcs dce80_tg_funcs = {
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.validate_timing = dce110_tg_validate_timing,
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.program_timing = program_timing,
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.enable_crtc = dce110_timing_generator_enable_crtc,
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.disable_crtc = dce110_timing_generator_disable_crtc,
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.is_counter_moving = dce110_timing_generator_is_counter_moving,
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.get_position = dce110_timing_generator_get_position,
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.get_frame_count = dce110_timing_generator_get_vblank_counter,
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.get_scanoutpos = dce110_timing_generator_get_crtc_scanoutpos,
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.set_early_control = dce110_timing_generator_set_early_control,
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.wait_for_state = dce110_tg_wait_for_state,
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.set_blank = dce110_tg_set_blank,
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.is_blanked = dce110_tg_is_blanked,
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.set_colors = dce110_tg_set_colors,
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.set_overscan_blank_color =
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dce110_timing_generator_set_overscan_color_black,
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.set_blank_color = dce110_timing_generator_program_blank_color,
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.disable_vga = dce110_timing_generator_disable_vga,
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.did_triggered_reset_occur =
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dce110_timing_generator_did_triggered_reset_occur,
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.setup_global_swap_lock =
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dce110_timing_generator_setup_global_swap_lock,
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.enable_reset_trigger = dce110_timing_generator_enable_reset_trigger,
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.disable_reset_trigger = dce110_timing_generator_disable_reset_trigger,
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.tear_down_global_swap_lock =
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dce110_timing_generator_tear_down_global_swap_lock,
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.set_drr = dce110_timing_generator_set_drr,
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.set_static_screen_control =
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dce110_timing_generator_set_static_screen_control,
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.set_test_pattern = dce110_timing_generator_set_test_pattern,
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.arm_vert_intr = dce110_arm_vert_intr,
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/* DCE8.0 overrides */
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.enable_advanced_request =
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dce80_timing_generator_enable_advanced_request,
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.configure_crc = dce110_configure_crc,
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.get_crc = dce110_get_crc,
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};
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void dce80_timing_generator_construct(
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struct dce110_timing_generator *tg110,
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struct dc_context *ctx,
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uint32_t instance,
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const struct dce110_timing_generator_offsets *offsets)
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{
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tg110->controller_id = CONTROLLER_ID_D0 + instance;
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tg110->base.inst = instance;
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tg110->offsets = *offsets;
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tg110->derived_offsets = reg_offsets[instance];
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tg110->base.funcs = &dce80_tg_funcs;
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tg110->base.ctx = ctx;
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tg110->base.bp = ctx->dc_bios;
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tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
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tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
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tg110->min_h_blank = 56;
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tg110->min_h_front_porch = 4;
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tg110->min_h_back_porch = 4;
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}
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