/*
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* Copyright 2012-16 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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/* TODO: this needs to be looked at, used by Stella's workaround*/
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#include "gmc/gmc_8_2_d.h"
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#include "gmc/gmc_8_2_sh_mask.h"
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#include "include/logger_interface.h"
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#include "inc/dce_calcs.h"
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#include "dce/dce_mem_input.h"
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static void set_flip_control(
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struct dce_mem_input *mem_input110,
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bool immediate)
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{
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uint32_t value = 0;
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value = dm_read_reg(
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mem_input110->base.ctx,
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mmUNP_FLIP_CONTROL);
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set_reg_field_value(value, 1,
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UNP_FLIP_CONTROL,
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GRPH_SURFACE_UPDATE_PENDING_MODE);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_FLIP_CONTROL,
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value);
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}
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/* chroma part */
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static void program_pri_addr_c(
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struct dce_mem_input *mem_input110,
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PHYSICAL_ADDRESS_LOC address)
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{
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uint32_t value = 0;
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uint32_t temp = 0;
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/*high register MUST be programmed first*/
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temp = address.high_part &
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK;
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set_reg_field_value(value, temp,
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
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GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,
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value);
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temp = 0;
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value = 0;
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temp = address.low_part >>
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT;
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set_reg_field_value(value, temp,
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
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GRPH_PRIMARY_SURFACE_ADDRESS_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,
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value);
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}
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/* luma part */
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static void program_pri_addr_l(
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struct dce_mem_input *mem_input110,
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PHYSICAL_ADDRESS_LOC address)
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{
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uint32_t value = 0;
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uint32_t temp = 0;
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/*high register MUST be programmed first*/
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temp = address.high_part &
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK;
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set_reg_field_value(value, temp,
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
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GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,
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value);
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temp = 0;
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value = 0;
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temp = address.low_part >>
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT;
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set_reg_field_value(value, temp,
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UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
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GRPH_PRIMARY_SURFACE_ADDRESS_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,
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value);
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}
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static void program_addr(
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struct dce_mem_input *mem_input110,
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const struct dc_plane_address *addr)
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{
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switch (addr->type) {
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case PLN_ADDR_TYPE_GRAPHICS:
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program_pri_addr_l(
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mem_input110,
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addr->grph.addr);
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break;
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case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
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program_pri_addr_c(
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mem_input110,
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addr->video_progressive.chroma_addr);
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program_pri_addr_l(
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mem_input110,
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addr->video_progressive.luma_addr);
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break;
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default:
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/* not supported */
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BREAK_TO_DEBUGGER();
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}
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}
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static void enable(struct dce_mem_input *mem_input110)
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{
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uint32_t value = 0;
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value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE);
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set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE);
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dm_write_reg(mem_input110->base.ctx,
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mmUNP_GRPH_ENABLE,
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value);
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}
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static void program_tiling(
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struct dce_mem_input *mem_input110,
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const union dc_tiling_info *info,
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const enum surface_pixel_format pixel_format)
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{
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uint32_t value = 0;
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set_reg_field_value(value, info->gfx8.num_banks,
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UNP_GRPH_CONTROL, GRPH_NUM_BANKS);
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set_reg_field_value(value, info->gfx8.bank_width,
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UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L);
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set_reg_field_value(value, info->gfx8.bank_height,
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UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L);
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set_reg_field_value(value, info->gfx8.tile_aspect,
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UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L);
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set_reg_field_value(value, info->gfx8.tile_split,
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UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L);
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set_reg_field_value(value, info->gfx8.tile_mode,
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UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L);
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set_reg_field_value(value, info->gfx8.pipe_config,
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UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG);
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set_reg_field_value(value, info->gfx8.array_mode,
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UNP_GRPH_CONTROL, GRPH_ARRAY_MODE);
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set_reg_field_value(value, 1,
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UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE);
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set_reg_field_value(value, 0,
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UNP_GRPH_CONTROL, GRPH_Z);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL,
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value);
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value = 0;
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set_reg_field_value(value, info->gfx8.bank_width_c,
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UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C);
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set_reg_field_value(value, info->gfx8.bank_height_c,
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UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C);
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set_reg_field_value(value, info->gfx8.tile_aspect_c,
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UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C);
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set_reg_field_value(value, info->gfx8.tile_split_c,
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UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C);
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set_reg_field_value(value, info->gfx8.tile_mode_c,
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UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL_C,
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value);
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}
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static void program_size_and_rotation(
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struct dce_mem_input *mem_input110,
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enum dc_rotation_angle rotation,
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const union plane_size *plane_size)
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{
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uint32_t value = 0;
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union plane_size local_size = *plane_size;
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if (rotation == ROTATION_ANGLE_90 ||
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rotation == ROTATION_ANGLE_270) {
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swap(local_size.video.luma_size.x,
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local_size.video.luma_size.y);
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swap(local_size.video.luma_size.width,
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local_size.video.luma_size.height);
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swap(local_size.video.chroma_size.x,
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local_size.video.chroma_size.y);
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swap(local_size.video.chroma_size.width,
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local_size.video.chroma_size.height);
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}
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value = 0;
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set_reg_field_value(value, local_size.video.luma_pitch,
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UNP_GRPH_PITCH_L, GRPH_PITCH_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PITCH_L,
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value);
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value = 0;
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set_reg_field_value(value, local_size.video.chroma_pitch,
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UNP_GRPH_PITCH_C, GRPH_PITCH_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_PITCH_C,
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value);
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value = 0;
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set_reg_field_value(value, 0,
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UNP_GRPH_X_START_L, GRPH_X_START_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_X_START_L,
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value);
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value = 0;
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set_reg_field_value(value, 0,
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UNP_GRPH_X_START_C, GRPH_X_START_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_X_START_C,
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value);
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value = 0;
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set_reg_field_value(value, 0,
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UNP_GRPH_Y_START_L, GRPH_Y_START_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_Y_START_L,
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value);
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value = 0;
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set_reg_field_value(value, 0,
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UNP_GRPH_Y_START_C, GRPH_Y_START_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_Y_START_C,
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value);
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value = 0;
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set_reg_field_value(value, local_size.video.luma_size.x +
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local_size.video.luma_size.width,
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UNP_GRPH_X_END_L, GRPH_X_END_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_X_END_L,
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value);
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value = 0;
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set_reg_field_value(value, local_size.video.chroma_size.x +
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local_size.video.chroma_size.width,
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UNP_GRPH_X_END_C, GRPH_X_END_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_X_END_C,
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value);
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value = 0;
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set_reg_field_value(value, local_size.video.luma_size.y +
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local_size.video.luma_size.height,
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UNP_GRPH_Y_END_L, GRPH_Y_END_L);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_Y_END_L,
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value);
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value = 0;
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set_reg_field_value(value, local_size.video.chroma_size.y +
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local_size.video.chroma_size.height,
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UNP_GRPH_Y_END_C, GRPH_Y_END_C);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_Y_END_C,
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value);
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value = 0;
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switch (rotation) {
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case ROTATION_ANGLE_90:
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set_reg_field_value(value, 3,
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UNP_HW_ROTATION, ROTATION_ANGLE);
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break;
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case ROTATION_ANGLE_180:
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set_reg_field_value(value, 2,
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UNP_HW_ROTATION, ROTATION_ANGLE);
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break;
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case ROTATION_ANGLE_270:
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set_reg_field_value(value, 1,
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UNP_HW_ROTATION, ROTATION_ANGLE);
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break;
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default:
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set_reg_field_value(value, 0,
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UNP_HW_ROTATION, ROTATION_ANGLE);
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break;
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}
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_HW_ROTATION,
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value);
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}
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static void program_pixel_format(
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struct dce_mem_input *mem_input110,
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enum surface_pixel_format format)
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{
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if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
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uint32_t value;
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uint8_t grph_depth;
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uint8_t grph_format;
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value = dm_read_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL);
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switch (format) {
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case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
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grph_depth = 0;
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grph_format = 0;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
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grph_depth = 1;
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grph_format = 1;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
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grph_depth = 2;
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grph_format = 0;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
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grph_depth = 2;
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grph_format = 1;
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break;
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
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case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
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case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
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grph_depth = 3;
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grph_format = 0;
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break;
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default:
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grph_depth = 2;
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grph_format = 0;
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break;
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}
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set_reg_field_value(
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value,
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grph_depth,
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UNP_GRPH_CONTROL,
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GRPH_DEPTH);
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set_reg_field_value(
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value,
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grph_format,
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UNP_GRPH_CONTROL,
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GRPH_FORMAT);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL,
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value);
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value = dm_read_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL_EXP);
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/* VIDEO FORMAT 0 */
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set_reg_field_value(
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value,
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0,
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UNP_GRPH_CONTROL_EXP,
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VIDEO_FORMAT);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL_EXP,
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value);
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} else {
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/* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */
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uint32_t value;
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uint8_t video_format;
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value = dm_read_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL_EXP);
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switch (format) {
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
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video_format = 2;
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break;
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case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
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video_format = 3;
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break;
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default:
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video_format = 0;
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break;
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}
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set_reg_field_value(
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value,
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video_format,
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UNP_GRPH_CONTROL_EXP,
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VIDEO_FORMAT);
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dm_write_reg(
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mem_input110->base.ctx,
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mmUNP_GRPH_CONTROL_EXP,
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value);
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}
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}
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bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input)
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{
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struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
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uint32_t value;
|
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value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE);
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if (get_reg_field_value(value, UNP_GRPH_UPDATE,
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GRPH_SURFACE_UPDATE_PENDING))
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return true;
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mem_input->current_address = mem_input->request_address;
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return false;
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}
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bool dce_mem_input_v_program_surface_flip_and_addr(
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struct mem_input *mem_input,
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const struct dc_plane_address *address,
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bool flip_immediate)
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{
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struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
|
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set_flip_control(mem_input110, flip_immediate);
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program_addr(mem_input110,
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address);
|
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mem_input->request_address = *address;
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return true;
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}
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/* Scatter Gather param tables */
|
static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = {
|
{ 8, 64, 64, 8, 8, 1, 4, 0, 0},
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{ 16, 64, 32, 8, 16, 1, 8, 0, 0},
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{ 32, 32, 32, 16, 16, 1, 8, 0, 0},
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{ 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */
|
};
|
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static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = {
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{ 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */
|
{ 16, 256, 8, 2, 0, 1, 0, 0, 0},
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{ 32, 128, 8, 4, 0, 1, 0, 0, 0},
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{ 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */
|
};
|
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static const unsigned int dvmm_Hw_Setting_Linear[4][9] = {
|
{ 8, 4096, 1, 8, 0, 1, 0, 0, 0},
|
{ 16, 2048, 1, 8, 0, 1, 0, 0, 0},
|
{ 32, 1024, 1, 8, 0, 1, 0, 0, 0},
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{ 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */
|
};
|
|
/* Helper to get table entry from surface info */
|
static const unsigned int *get_dvmm_hw_setting(
|
union dc_tiling_info *tiling_info,
|
enum surface_pixel_format format,
|
bool chroma)
|
{
|
enum bits_per_pixel {
|
bpp_8 = 0,
|
bpp_16,
|
bpp_32,
|
bpp_64
|
} bpp;
|
|
if (format >= SURFACE_PIXEL_FORMAT_INVALID)
|
bpp = bpp_32;
|
else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
|
bpp = chroma ? bpp_16 : bpp_8;
|
else
|
bpp = bpp_8;
|
|
switch (tiling_info->gfx8.array_mode) {
|
case DC_ARRAY_1D_TILED_THIN1:
|
case DC_ARRAY_1D_TILED_THICK:
|
case DC_ARRAY_PRT_TILED_THIN1:
|
return dvmm_Hw_Setting_1DTiling[bpp];
|
case DC_ARRAY_2D_TILED_THIN1:
|
case DC_ARRAY_2D_TILED_THICK:
|
case DC_ARRAY_2D_TILED_X_THICK:
|
case DC_ARRAY_PRT_2D_TILED_THIN1:
|
case DC_ARRAY_PRT_2D_TILED_THICK:
|
return dvmm_Hw_Setting_2DTiling[bpp];
|
case DC_ARRAY_LINEAR_GENERAL:
|
case DC_ARRAY_LINEAR_ALLIGNED:
|
return dvmm_Hw_Setting_Linear[bpp];
|
default:
|
return dvmm_Hw_Setting_2DTiling[bpp];
|
}
|
}
|
|
void dce_mem_input_v_program_pte_vm(
|
struct mem_input *mem_input,
|
enum surface_pixel_format format,
|
union dc_tiling_info *tiling_info,
|
enum dc_rotation_angle rotation)
|
{
|
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
|
const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false);
|
const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true);
|
|
unsigned int page_width = 0;
|
unsigned int page_height = 0;
|
unsigned int page_width_chroma = 0;
|
unsigned int page_height_chroma = 0;
|
unsigned int temp_page_width = pte[1];
|
unsigned int temp_page_height = pte[2];
|
unsigned int min_pte_before_flip = 0;
|
unsigned int min_pte_before_flip_chroma = 0;
|
uint32_t value = 0;
|
|
while ((temp_page_width >>= 1) != 0)
|
page_width++;
|
while ((temp_page_height >>= 1) != 0)
|
page_height++;
|
|
temp_page_width = pte_chroma[1];
|
temp_page_height = pte_chroma[2];
|
while ((temp_page_width >>= 1) != 0)
|
page_width_chroma++;
|
while ((temp_page_height >>= 1) != 0)
|
page_height_chroma++;
|
|
switch (rotation) {
|
case ROTATION_ANGLE_90:
|
case ROTATION_ANGLE_270:
|
min_pte_before_flip = pte[4];
|
min_pte_before_flip_chroma = pte_chroma[4];
|
break;
|
default:
|
min_pte_before_flip = pte[3];
|
min_pte_before_flip_chroma = pte_chroma[3];
|
break;
|
}
|
|
value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT);
|
/* TODO: un-hardcode requestlimit */
|
set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L);
|
set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C);
|
dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value);
|
|
value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL);
|
set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH);
|
set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT);
|
set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP);
|
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value);
|
|
value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL);
|
set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK);
|
set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING);
|
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value);
|
|
value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C);
|
set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C);
|
set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C);
|
set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C);
|
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value);
|
|
value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C);
|
set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C);
|
set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C);
|
dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value);
|
}
|
|
void dce_mem_input_v_program_surface_config(
|
struct mem_input *mem_input,
|
enum surface_pixel_format format,
|
union dc_tiling_info *tiling_info,
|
union plane_size *plane_size,
|
enum dc_rotation_angle rotation,
|
struct dc_plane_dcc_param *dcc,
|
bool horizotal_mirror)
|
{
|
struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input);
|
|
enable(mem_input110);
|
program_tiling(mem_input110, tiling_info, format);
|
program_size_and_rotation(mem_input110, rotation, plane_size);
|
program_pixel_format(mem_input110, format);
|
}
|
|
static void program_urgency_watermark(
|
const struct dc_context *ctx,
|
const uint32_t urgency_addr,
|
const uint32_t wm_addr,
|
struct dce_watermarks marks_low,
|
uint32_t total_dest_line_time_ns)
|
{
|
/* register value */
|
uint32_t urgency_cntl = 0;
|
uint32_t wm_mask_cntl = 0;
|
|
/*Write mask to enable reading/writing of watermark set A*/
|
wm_mask_cntl = dm_read_reg(ctx, wm_addr);
|
set_reg_field_value(wm_mask_cntl,
|
1,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
URGENCY_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_addr, wm_mask_cntl);
|
|
urgency_cntl = dm_read_reg(ctx, urgency_addr);
|
|
set_reg_field_value(
|
urgency_cntl,
|
marks_low.a_mark,
|
DPGV0_PIPE_URGENCY_CONTROL,
|
URGENCY_LOW_WATERMARK);
|
|
set_reg_field_value(
|
urgency_cntl,
|
total_dest_line_time_ns,
|
DPGV0_PIPE_URGENCY_CONTROL,
|
URGENCY_HIGH_WATERMARK);
|
dm_write_reg(ctx, urgency_addr, urgency_cntl);
|
|
/*Write mask to enable reading/writing of watermark set B*/
|
wm_mask_cntl = dm_read_reg(ctx, wm_addr);
|
set_reg_field_value(wm_mask_cntl,
|
2,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
URGENCY_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_addr, wm_mask_cntl);
|
|
urgency_cntl = dm_read_reg(ctx, urgency_addr);
|
|
set_reg_field_value(urgency_cntl,
|
marks_low.b_mark,
|
DPGV0_PIPE_URGENCY_CONTROL,
|
URGENCY_LOW_WATERMARK);
|
|
set_reg_field_value(urgency_cntl,
|
total_dest_line_time_ns,
|
DPGV0_PIPE_URGENCY_CONTROL,
|
URGENCY_HIGH_WATERMARK);
|
|
dm_write_reg(ctx, urgency_addr, urgency_cntl);
|
}
|
|
static void program_urgency_watermark_l(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks_low,
|
uint32_t total_dest_line_time_ns)
|
{
|
program_urgency_watermark(
|
ctx,
|
mmDPGV0_PIPE_URGENCY_CONTROL,
|
mmDPGV0_WATERMARK_MASK_CONTROL,
|
marks_low,
|
total_dest_line_time_ns);
|
}
|
|
static void program_urgency_watermark_c(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks_low,
|
uint32_t total_dest_line_time_ns)
|
{
|
program_urgency_watermark(
|
ctx,
|
mmDPGV1_PIPE_URGENCY_CONTROL,
|
mmDPGV1_WATERMARK_MASK_CONTROL,
|
marks_low,
|
total_dest_line_time_ns);
|
}
|
|
static void program_stutter_watermark(
|
const struct dc_context *ctx,
|
const uint32_t stutter_addr,
|
const uint32_t wm_addr,
|
struct dce_watermarks marks)
|
{
|
/* register value */
|
uint32_t stutter_cntl = 0;
|
uint32_t wm_mask_cntl = 0;
|
|
/*Write mask to enable reading/writing of watermark set A*/
|
|
wm_mask_cntl = dm_read_reg(ctx, wm_addr);
|
set_reg_field_value(wm_mask_cntl,
|
1,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_addr, wm_mask_cntl);
|
|
stutter_cntl = dm_read_reg(ctx, stutter_addr);
|
|
if (ctx->dc->debug.disable_stutter) {
|
set_reg_field_value(stutter_cntl,
|
0,
|
DPGV0_PIPE_STUTTER_CONTROL,
|
STUTTER_ENABLE);
|
} else {
|
set_reg_field_value(stutter_cntl,
|
1,
|
DPGV0_PIPE_STUTTER_CONTROL,
|
STUTTER_ENABLE);
|
}
|
|
set_reg_field_value(stutter_cntl,
|
1,
|
DPGV0_PIPE_STUTTER_CONTROL,
|
STUTTER_IGNORE_FBC);
|
|
/*Write watermark set A*/
|
set_reg_field_value(stutter_cntl,
|
marks.a_mark,
|
DPGV0_PIPE_STUTTER_CONTROL,
|
STUTTER_EXIT_SELF_REFRESH_WATERMARK);
|
dm_write_reg(ctx, stutter_addr, stutter_cntl);
|
|
/*Write mask to enable reading/writing of watermark set B*/
|
wm_mask_cntl = dm_read_reg(ctx, wm_addr);
|
set_reg_field_value(wm_mask_cntl,
|
2,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_addr, wm_mask_cntl);
|
|
stutter_cntl = dm_read_reg(ctx, stutter_addr);
|
/*Write watermark set B*/
|
set_reg_field_value(stutter_cntl,
|
marks.b_mark,
|
DPGV0_PIPE_STUTTER_CONTROL,
|
STUTTER_EXIT_SELF_REFRESH_WATERMARK);
|
dm_write_reg(ctx, stutter_addr, stutter_cntl);
|
}
|
|
static void program_stutter_watermark_l(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks)
|
{
|
program_stutter_watermark(ctx,
|
mmDPGV0_PIPE_STUTTER_CONTROL,
|
mmDPGV0_WATERMARK_MASK_CONTROL,
|
marks);
|
}
|
|
static void program_stutter_watermark_c(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks)
|
{
|
program_stutter_watermark(ctx,
|
mmDPGV1_PIPE_STUTTER_CONTROL,
|
mmDPGV1_WATERMARK_MASK_CONTROL,
|
marks);
|
}
|
|
static void program_nbp_watermark(
|
const struct dc_context *ctx,
|
const uint32_t wm_mask_ctrl_addr,
|
const uint32_t nbp_pstate_ctrl_addr,
|
struct dce_watermarks marks)
|
{
|
uint32_t value;
|
|
/* Write mask to enable reading/writing of watermark set A */
|
|
value = dm_read_reg(ctx, wm_mask_ctrl_addr);
|
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
NB_PSTATE_CHANGE_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_mask_ctrl_addr, value);
|
|
value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
|
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_ENABLE);
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
|
dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
|
|
/* Write watermark set A */
|
value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
|
set_reg_field_value(
|
value,
|
marks.a_mark,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_WATERMARK);
|
dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
|
|
/* Write mask to enable reading/writing of watermark set B */
|
value = dm_read_reg(ctx, wm_mask_ctrl_addr);
|
set_reg_field_value(
|
value,
|
2,
|
DPGV0_WATERMARK_MASK_CONTROL,
|
NB_PSTATE_CHANGE_WATERMARK_MASK);
|
dm_write_reg(ctx, wm_mask_ctrl_addr, value);
|
|
value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_ENABLE);
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_URGENT_DURING_REQUEST);
|
set_reg_field_value(
|
value,
|
1,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST);
|
dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
|
|
/* Write watermark set B */
|
value = dm_read_reg(ctx, nbp_pstate_ctrl_addr);
|
set_reg_field_value(
|
value,
|
marks.b_mark,
|
DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
NB_PSTATE_CHANGE_WATERMARK);
|
dm_write_reg(ctx, nbp_pstate_ctrl_addr, value);
|
}
|
|
static void program_nbp_watermark_l(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks)
|
{
|
program_nbp_watermark(ctx,
|
mmDPGV0_WATERMARK_MASK_CONTROL,
|
mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
marks);
|
}
|
|
static void program_nbp_watermark_c(
|
const struct dc_context *ctx,
|
struct dce_watermarks marks)
|
{
|
program_nbp_watermark(ctx,
|
mmDPGV1_WATERMARK_MASK_CONTROL,
|
mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL,
|
marks);
|
}
|
|
void dce_mem_input_v_program_display_marks(
|
struct mem_input *mem_input,
|
struct dce_watermarks nbp,
|
struct dce_watermarks stutter,
|
struct dce_watermarks stutter_enter,
|
struct dce_watermarks urgent,
|
uint32_t total_dest_line_time_ns)
|
{
|
program_urgency_watermark_l(
|
mem_input->ctx,
|
urgent,
|
total_dest_line_time_ns);
|
|
program_nbp_watermark_l(
|
mem_input->ctx,
|
nbp);
|
|
program_stutter_watermark_l(
|
mem_input->ctx,
|
stutter);
|
|
}
|
|
void dce_mem_input_program_chroma_display_marks(
|
struct mem_input *mem_input,
|
struct dce_watermarks nbp,
|
struct dce_watermarks stutter,
|
struct dce_watermarks urgent,
|
uint32_t total_dest_line_time_ns)
|
{
|
program_urgency_watermark_c(
|
mem_input->ctx,
|
urgent,
|
total_dest_line_time_ns);
|
|
program_nbp_watermark_c(
|
mem_input->ctx,
|
nbp);
|
|
program_stutter_watermark_c(
|
mem_input->ctx,
|
stutter);
|
}
|
|
void dce110_allocate_mem_input_v(
|
struct mem_input *mi,
|
uint32_t h_total,/* for current stream */
|
uint32_t v_total,/* for current stream */
|
uint32_t pix_clk_khz,/* for current stream */
|
uint32_t total_stream_num)
|
{
|
uint32_t addr;
|
uint32_t value;
|
uint32_t pix_dur;
|
if (pix_clk_khz != 0) {
|
addr = mmDPGV0_PIPE_ARBITRATION_CONTROL1;
|
value = dm_read_reg(mi->ctx, addr);
|
pix_dur = 1000000000ULL / pix_clk_khz;
|
set_reg_field_value(
|
value,
|
pix_dur,
|
DPGV0_PIPE_ARBITRATION_CONTROL1,
|
PIXEL_DURATION);
|
dm_write_reg(mi->ctx, addr, value);
|
|
addr = mmDPGV1_PIPE_ARBITRATION_CONTROL1;
|
value = dm_read_reg(mi->ctx, addr);
|
pix_dur = 1000000000ULL / pix_clk_khz;
|
set_reg_field_value(
|
value,
|
pix_dur,
|
DPGV1_PIPE_ARBITRATION_CONTROL1,
|
PIXEL_DURATION);
|
dm_write_reg(mi->ctx, addr, value);
|
|
addr = mmDPGV0_PIPE_ARBITRATION_CONTROL2;
|
value = 0x4000800;
|
dm_write_reg(mi->ctx, addr, value);
|
|
addr = mmDPGV1_PIPE_ARBITRATION_CONTROL2;
|
value = 0x4000800;
|
dm_write_reg(mi->ctx, addr, value);
|
}
|
|
}
|
|
void dce110_free_mem_input_v(
|
struct mem_input *mi,
|
uint32_t total_stream_num)
|
{
|
}
|
|
static const struct mem_input_funcs dce110_mem_input_v_funcs = {
|
.mem_input_program_display_marks =
|
dce_mem_input_v_program_display_marks,
|
.mem_input_program_chroma_display_marks =
|
dce_mem_input_program_chroma_display_marks,
|
.allocate_mem_input = dce110_allocate_mem_input_v,
|
.free_mem_input = dce110_free_mem_input_v,
|
.mem_input_program_surface_flip_and_addr =
|
dce_mem_input_v_program_surface_flip_and_addr,
|
.mem_input_program_pte_vm =
|
dce_mem_input_v_program_pte_vm,
|
.mem_input_program_surface_config =
|
dce_mem_input_v_program_surface_config,
|
.mem_input_is_flip_pending =
|
dce_mem_input_v_is_surface_pending
|
};
|
/*****************************************/
|
/* Constructor, Destructor */
|
/*****************************************/
|
|
void dce110_mem_input_v_construct(
|
struct dce_mem_input *dce_mi,
|
struct dc_context *ctx)
|
{
|
dce_mi->base.funcs = &dce110_mem_input_v_funcs;
|
dce_mi->base.ctx = ctx;
|
}
|
