/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dce/dce_11_0_d.h"
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#include "dce/dce_11_0_sh_mask.h"
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#include "gmc/gmc_8_2_sh_mask.h"
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#include "gmc/gmc_8_2_d.h"
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#include "include/logger_interface.h"
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#include "dce110_compressor.h"
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#define DC_LOGGER \
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cp110->base.ctx->logger
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#define DCP_REG(reg)\
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(reg + cp110->offsets.dcp_offset)
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#define DMIF_REG(reg)\
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(reg + cp110->offsets.dmif_offset)
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static const struct dce110_compressor_reg_offsets reg_offsets[] = {
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{
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.dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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.dmif_offset =
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(mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
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- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
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},
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{
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.dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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.dmif_offset =
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(mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
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- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
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},
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{
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.dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
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.dmif_offset =
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(mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
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- mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
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}
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};
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static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
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enum fbc_idle_force {
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/* Bit 0 - Display registers updated */
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FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
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/* Bit 2 - FBC_GRPH_COMP_EN register updated */
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FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
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/* Bit 3 - FBC_SRC_SEL register updated */
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FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
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/* Bit 4 - FBC_MIN_COMPRESSION register updated */
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FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
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/* Bit 5 - FBC_ALPHA_COMP_EN register updated */
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FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
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/* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
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FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
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/* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
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FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
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/* Bit 24 - Memory write to region 0 defined by MC registers. */
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FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
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/* Bit 25 - Memory write to region 1 defined by MC registers */
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FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
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/* Bit 26 - Memory write to region 2 defined by MC registers */
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FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
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/* Bit 27 - Memory write to region 3 defined by MC registers. */
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FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
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/* Bit 28 - Memory write from any client other than MCIF */
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FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
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/* Bit 29 - CG statics screen signal is inactive */
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FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
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};
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static uint32_t align_to_chunks_number_per_line(uint32_t pixels)
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{
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return 256 * ((pixels + 255) / 256);
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}
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static void reset_lb_on_vblank(struct dc_context *ctx)
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{
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uint32_t value, frame_count;
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uint32_t retry = 0;
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uint32_t status_pos =
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dm_read_reg(ctx, mmCRTC_STATUS_POSITION);
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/* Only if CRTC is enabled and counter is moving we wait for one frame. */
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if (status_pos != dm_read_reg(ctx, mmCRTC_STATUS_POSITION)) {
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/* Resetting LB on VBlank */
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value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
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set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
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set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
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dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
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frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT);
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for (retry = 10000; retry > 0; retry--) {
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if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT))
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break;
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udelay(10);
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}
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if (!retry)
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dm_error("Frame count did not increase for 100ms.\n");
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/* Resetting LB on VBlank */
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value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL);
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set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL);
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set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2);
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dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value);
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}
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}
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static void wait_for_fbc_state_changed(
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struct dce110_compressor *cp110,
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bool enabled)
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{
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uint32_t counter = 0;
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uint32_t addr = mmFBC_STATUS;
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uint32_t value;
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while (counter < 1000) {
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value = dm_read_reg(cp110->base.ctx, addr);
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if (get_reg_field_value(
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value,
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FBC_STATUS,
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FBC_ENABLE_STATUS) == enabled)
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break;
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udelay(100);
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counter++;
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}
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if (counter == 1000) {
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DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not applied",
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__func__);
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} else {
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DC_LOG_SYNC("FBC status changed to %d", enabled);
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}
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}
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void dce110_compressor_power_up_fbc(struct compressor *compressor)
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{
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uint32_t value;
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uint32_t addr;
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addr = mmFBC_CNTL;
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value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
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set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
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set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
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if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
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/* HW needs to do power measurement comparison. */
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set_reg_field_value(
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value,
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0,
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FBC_CNTL,
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FBC_COMP_CLK_GATE_EN);
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}
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dm_write_reg(compressor->ctx, addr, value);
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addr = mmFBC_COMP_MODE;
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value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
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set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
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set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
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dm_write_reg(compressor->ctx, addr, value);
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addr = mmFBC_COMP_CNTL;
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value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
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dm_write_reg(compressor->ctx, addr, value);
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/*FBC_MIN_COMPRESSION 0 ==> 2:1 */
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/* 1 ==> 4:1 */
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/* 2 ==> 8:1 */
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/* 0xF ==> 1:1 */
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set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
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dm_write_reg(compressor->ctx, addr, value);
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compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
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value = 0;
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dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
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value = 0xFFFFFF;
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dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
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}
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void dce110_compressor_enable_fbc(
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struct compressor *compressor,
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struct compr_addr_and_pitch_params *params)
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{
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struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
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if (compressor->options.bits.FBC_SUPPORT &&
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(!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) {
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uint32_t addr;
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uint32_t value, misc_value;
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addr = mmFBC_CNTL;
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value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
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set_reg_field_value(
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value,
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params->inst,
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FBC_CNTL, FBC_SRC_SEL);
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dm_write_reg(compressor->ctx, addr, value);
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/* Keep track of enum controller_id FBC is attached to */
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compressor->is_enabled = true;
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compressor->attached_inst = params->inst;
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cp110->offsets = reg_offsets[params->inst];
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/* Toggle it as there is bug in HW */
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set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
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dm_write_reg(compressor->ctx, addr, value);
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/* FBC usage with scatter & gather for dce110 */
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misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC);
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set_reg_field_value(misc_value, 1,
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FBC_MISC, FBC_INVALIDATE_ON_ERROR);
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set_reg_field_value(misc_value, 1,
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FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR);
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set_reg_field_value(misc_value, 0x14,
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FBC_MISC, FBC_SLOW_REQ_INTERVAL);
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dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value);
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/* Enable FBC */
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set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
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dm_write_reg(compressor->ctx, addr, value);
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wait_for_fbc_state_changed(cp110, true);
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}
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}
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void dce110_compressor_disable_fbc(struct compressor *compressor)
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{
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struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
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if (compressor->options.bits.FBC_SUPPORT) {
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if (dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
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uint32_t reg_data;
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/* Turn off compression */
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reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
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set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
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dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
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/* Reset enum controller_id to undefined */
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compressor->attached_inst = 0;
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compressor->is_enabled = false;
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wait_for_fbc_state_changed(cp110, false);
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}
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/* Sync line buffer - dce100/110 only*/
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reset_lb_on_vblank(compressor->ctx);
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}
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}
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bool dce110_compressor_is_fbc_enabled_in_hw(
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struct compressor *compressor,
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uint32_t *inst)
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{
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/* Check the hardware register */
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uint32_t value;
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value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
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if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
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if (inst != NULL)
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*inst = compressor->attached_inst;
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return true;
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}
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value = dm_read_reg(compressor->ctx, mmFBC_MISC);
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if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
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value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
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if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
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if (inst != NULL)
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*inst =
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compressor->attached_inst;
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return true;
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}
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}
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return false;
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}
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void dce110_compressor_program_compressed_surface_address_and_pitch(
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struct compressor *compressor,
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struct compr_addr_and_pitch_params *params)
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{
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struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
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uint32_t value = 0;
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uint32_t fbc_pitch = 0;
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uint32_t compressed_surf_address_low_part =
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compressor->compr_surface_address.addr.low_part;
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/* Clear content first. */
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dm_write_reg(
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compressor->ctx,
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DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
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0);
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dm_write_reg(compressor->ctx,
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DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
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/* Write address, HIGH has to be first. */
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dm_write_reg(compressor->ctx,
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DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
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compressor->compr_surface_address.addr.high_part);
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dm_write_reg(compressor->ctx,
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DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
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compressed_surf_address_low_part);
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fbc_pitch = align_to_chunks_number_per_line(params->source_view_width);
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if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
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fbc_pitch = fbc_pitch / 8;
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else
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DC_LOG_WARNING("%s: Unexpected DCE11 compression ratio",
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__func__);
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/* Clear content first. */
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dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
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/* Write FBC Pitch. */
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set_reg_field_value(
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value,
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fbc_pitch,
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GRPH_COMPRESS_PITCH,
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GRPH_COMPRESS_PITCH);
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dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
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}
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void dce110_compressor_set_fbc_invalidation_triggers(
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struct compressor *compressor,
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uint32_t fbc_trigger)
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{
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/* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
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* for DCE 11 regions cannot be used - does not work with S/G
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*/
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uint32_t addr = mmFBC_CLIENT_REGION_MASK;
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uint32_t value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(
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value,
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0,
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FBC_CLIENT_REGION_MASK,
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FBC_MEMORY_REGION_MASK);
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dm_write_reg(compressor->ctx, addr, value);
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/* Setup events when to clear all CSM entries (effectively marking
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* current compressed data invalid)
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* For DCE 11 CSM metadata 11111 means - "Not Compressed"
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* Used as the initial value of the metadata sent to the compressor
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* after invalidation, to indicate that the compressor should attempt
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* to compress all chunks on the current pass. Also used when the chunk
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* is not successfully written to memory.
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* When this CSM value is detected, FBC reads from the uncompressed
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* buffer. Set events according to passed in value, these events are
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* valid for DCE11:
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* - bit 0 - display register updated
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* - bit 28 - memory write from any client except from MCIF
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* - bit 29 - CG static screen signal is inactive
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* In addition, DCE11.1 also needs to set new DCE11.1 specific events
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* that are used to trigger invalidation on certain register changes,
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* for example enabling of Alpha Compression may trigger invalidation of
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* FBC once bit is set. These events are as follows:
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* - Bit 2 - FBC_GRPH_COMP_EN register updated
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* - Bit 3 - FBC_SRC_SEL register updated
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* - Bit 4 - FBC_MIN_COMPRESSION register updated
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* - Bit 5 - FBC_ALPHA_COMP_EN register updated
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* - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
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* - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
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*/
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addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
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value = dm_read_reg(compressor->ctx, addr);
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set_reg_field_value(
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value,
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fbc_trigger |
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FBC_IDLE_FORCE_GRPH_COMP_EN |
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FBC_IDLE_FORCE_SRC_SEL_CHANGE |
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FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
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FBC_IDLE_FORCE_ALPHA_COMP_EN |
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FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
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FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
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FBC_IDLE_FORCE_CLEAR_MASK,
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FBC_IDLE_FORCE_CLEAR_MASK);
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dm_write_reg(compressor->ctx, addr, value);
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}
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struct compressor *dce110_compressor_create(struct dc_context *ctx)
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{
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struct dce110_compressor *cp110 =
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kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL);
|
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if (!cp110)
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return NULL;
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dce110_compressor_construct(cp110, ctx);
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return &cp110->base;
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}
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void dce110_compressor_destroy(struct compressor **compressor)
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{
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kfree(TO_DCE110_COMPRESSOR(*compressor));
|
*compressor = NULL;
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}
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bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info,
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struct fbc_requested_compressed_size size)
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{
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bool result = false;
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unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y;
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get_max_support_fbc_buffersize(&max_x, &max_y);
|
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if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) {
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/*
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* For DCE11 here use Max HW supported size: HW Support up to 3840x2400 resolution
|
* or 18000 chunks.
|
*/
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size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4; /* (For FBC when LPT not supported). */
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size.preferred_size_alignment = size.min_size_alignment = 0x100; /* For FBC when LPT not supported */
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size.bits.preferred_must_be_framebuffer_pool = 1;
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size.bits.min_must_be_framebuffer_pool = 1;
|
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result = true;
|
}
|
/*
|
* Maybe to add registry key support with optional size here to override above
|
* for debugging purposes
|
*/
|
|
return result;
|
}
|
|
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void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y)
|
{
|
*max_x = FBC_MAX_X;
|
*max_y = FBC_MAX_Y;
|
|
/* if (m_smallLocalFrameBufferMemory == 1)
|
* {
|
* *max_x = FBC_MAX_X_SG;
|
* *max_y = FBC_MAX_Y_SG;
|
* }
|
*/
|
}
|
|
|
unsigned int controller_id_to_index(enum controller_id controller_id)
|
{
|
unsigned int index = 0;
|
|
switch (controller_id) {
|
case CONTROLLER_ID_D0:
|
index = 0;
|
break;
|
case CONTROLLER_ID_D1:
|
index = 1;
|
break;
|
case CONTROLLER_ID_D2:
|
index = 2;
|
break;
|
case CONTROLLER_ID_D3:
|
index = 3;
|
break;
|
default:
|
break;
|
}
|
return index;
|
}
|
|
|
static const struct compressor_funcs dce110_compressor_funcs = {
|
.power_up_fbc = dce110_compressor_power_up_fbc,
|
.enable_fbc = dce110_compressor_enable_fbc,
|
.disable_fbc = dce110_compressor_disable_fbc,
|
.set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers,
|
.surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch,
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.is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw
|
};
|
|
|
void dce110_compressor_construct(struct dce110_compressor *compressor,
|
struct dc_context *ctx)
|
{
|
|
compressor->base.options.raw = 0;
|
compressor->base.options.bits.FBC_SUPPORT = true;
|
|
/* for dce 11 always use one dram channel for lpt */
|
compressor->base.lpt_channels_num = 1;
|
compressor->base.options.bits.DUMMY_BACKEND = false;
|
|
/*
|
* check if this system has more than 1 dram channel; if only 1 then lpt
|
* should not be supported
|
*/
|
|
|
compressor->base.options.bits.CLK_GATING_DISABLED = false;
|
|
compressor->base.ctx = ctx;
|
compressor->base.embedded_panel_h_size = 0;
|
compressor->base.embedded_panel_v_size = 0;
|
compressor->base.memory_bus_width = ctx->asic_id.vram_width;
|
compressor->base.allocated_size = 0;
|
compressor->base.preferred_requested_size = 0;
|
compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
|
compressor->base.banks_num = 0;
|
compressor->base.raw_size = 0;
|
compressor->base.channel_interleave_size = 0;
|
compressor->base.dram_channels_num = 0;
|
compressor->base.lpt_channels_num = 0;
|
compressor->base.attached_inst = 0;
|
compressor->base.is_enabled = false;
|
compressor->base.funcs = &dce110_compressor_funcs;
|
|
}
|
