/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_TYPES_H_
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#define DC_TYPES_H_
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#include "os_types.h"
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#include "fixed31_32.h"
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#include "irq_types.h"
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#include "dc_dp_types.h"
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#include "dc_hw_types.h"
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#include "dal_types.h"
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#include "grph_object_defs.h"
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/* forward declarations */
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struct dc_plane_state;
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struct dc_stream_state;
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struct dc_link;
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struct dc_sink;
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struct dal;
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/********************************
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* Environment definitions
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********************************/
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enum dce_environment {
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DCE_ENV_PRODUCTION_DRV = 0,
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/* Emulation on FPGA, in "Maximus" System.
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* This environment enforces that *only* DC registers accessed.
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* (access to non-DC registers will hang FPGA) */
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DCE_ENV_FPGA_MAXIMUS,
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/* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
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* requirements of Diagnostics team. */
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DCE_ENV_DIAG
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};
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/* Note: use these macro definitions instead of direct comparison! */
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#define IS_FPGA_MAXIMUS_DC(dce_environment) \
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(dce_environment == DCE_ENV_FPGA_MAXIMUS)
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#define IS_DIAG_DC(dce_environment) \
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(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
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struct hw_asic_id {
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uint32_t chip_id;
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uint32_t chip_family;
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uint32_t pci_revision_id;
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uint32_t hw_internal_rev;
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uint32_t vram_type;
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uint32_t vram_width;
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uint32_t feature_flags;
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uint32_t fake_paths_num;
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void *atombios_base_address;
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};
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struct dc_context {
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struct dc *dc;
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void *driver_context; /* e.g. amdgpu_device */
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void *cgs_device;
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enum dce_environment dce_environment;
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struct hw_asic_id asic_id;
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/* todo: below should probably move to dc. to facilitate removal
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* of AS we will store these here
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*/
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enum dce_version dce_version;
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struct dc_bios *dc_bios;
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bool created_bios;
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struct gpio_service *gpio_service;
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struct i2caux *i2caux;
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uint32_t dc_sink_id_count;
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uint64_t fbc_gpu_addr;
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};
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#define DC_MAX_EDID_BUFFER_SIZE 512
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#define EDID_BLOCK_SIZE 128
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#define MAX_SURFACE_NUM 4
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#define NUM_PIXEL_FORMATS 10
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#include "dc_ddc_types.h"
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enum tiling_mode {
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TILING_MODE_INVALID,
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TILING_MODE_LINEAR,
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TILING_MODE_TILED,
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TILING_MODE_COUNT
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};
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enum view_3d_format {
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VIEW_3D_FORMAT_NONE = 0,
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VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
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VIEW_3D_FORMAT_SIDE_BY_SIDE,
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VIEW_3D_FORMAT_TOP_AND_BOTTOM,
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VIEW_3D_FORMAT_COUNT,
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VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
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};
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enum plane_stereo_format {
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PLANE_STEREO_FORMAT_NONE = 0,
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PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
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PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
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PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
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PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
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PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
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PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
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};
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/* TODO: Find way to calculate number of bits
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* Please increase if pixel_format enum increases
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* num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32
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*/
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enum dc_edid_connector_type {
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DC_EDID_CONNECTOR_UNKNOWN = 0,
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DC_EDID_CONNECTOR_ANALOG = 1,
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DC_EDID_CONNECTOR_DIGITAL = 10,
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DC_EDID_CONNECTOR_DVI = 11,
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DC_EDID_CONNECTOR_HDMIA = 12,
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DC_EDID_CONNECTOR_MDDI = 14,
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DC_EDID_CONNECTOR_DISPLAYPORT = 15
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};
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enum dc_edid_status {
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EDID_OK,
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EDID_BAD_INPUT,
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EDID_NO_RESPONSE,
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EDID_BAD_CHECKSUM,
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EDID_THE_SAME,
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};
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/* audio capability from EDID*/
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struct dc_cea_audio_mode {
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uint8_t format_code; /* ucData[0] [6:3]*/
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uint8_t channel_count; /* ucData[0] [2:0]*/
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uint8_t sample_rate; /* ucData[1]*/
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union {
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uint8_t sample_size; /* for LPCM*/
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/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
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uint8_t max_bit_rate;
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uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
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};
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};
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struct dc_edid {
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uint32_t length;
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uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
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};
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/* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION
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* is used. In this case we assume speaker location are: front left, front
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* right and front center. */
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#define DEFAULT_SPEAKER_LOCATION 5
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#define DC_MAX_AUDIO_DESC_COUNT 16
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#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
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union display_content_support {
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unsigned int raw;
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struct {
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unsigned int valid_content_type :1;
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unsigned int game_content :1;
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unsigned int cinema_content :1;
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unsigned int photo_content :1;
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unsigned int graphics_content :1;
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unsigned int reserved :27;
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} bits;
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};
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struct dc_panel_patch {
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unsigned int dppowerup_delay;
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unsigned int extra_t12_ms;
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};
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struct dc_edid_caps {
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/* sink identification */
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uint16_t manufacturer_id;
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uint16_t product_id;
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uint32_t serial_number;
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uint8_t manufacture_week;
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uint8_t manufacture_year;
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uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
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/* audio caps */
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uint8_t speaker_flags;
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uint32_t audio_mode_count;
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struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
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uint32_t audio_latency;
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uint32_t video_latency;
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union display_content_support content_support;
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uint8_t qs_bit;
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uint8_t qy_bit;
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/*HDMI 2.0 caps*/
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bool lte_340mcsc_scramble;
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bool edid_hdmi;
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bool hdr_supported;
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struct dc_panel_patch panel_patch;
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};
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struct view {
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uint32_t width;
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uint32_t height;
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};
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struct dc_mode_flags {
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/* note: part of refresh rate flag*/
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uint32_t INTERLACE :1;
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/* native display timing*/
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uint32_t NATIVE :1;
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/* preferred is the recommended mode, one per display */
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uint32_t PREFERRED :1;
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/* true if this mode should use reduced blanking timings
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*_not_ related to the Reduced Blanking adjustment*/
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uint32_t REDUCED_BLANKING :1;
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/* note: part of refreshrate flag*/
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uint32_t VIDEO_OPTIMIZED_RATE :1;
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/* should be reported to upper layers as mode_flags*/
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uint32_t PACKED_PIXEL_FORMAT :1;
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/*< preferred view*/
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uint32_t PREFERRED_VIEW :1;
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/* this timing should be used only in tiled mode*/
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uint32_t TILED_MODE :1;
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uint32_t DSE_MODE :1;
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/* Refresh rate divider when Miracast sink is using a
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different rate than the output display device
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Must be zero for wired displays and non-zero for
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Miracast displays*/
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uint32_t MIRACAST_REFRESH_DIVIDER;
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};
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enum dc_timing_source {
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TIMING_SOURCE_UNDEFINED,
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/* explicitly specifed by user, most important*/
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TIMING_SOURCE_USER_FORCED,
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TIMING_SOURCE_USER_OVERRIDE,
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TIMING_SOURCE_CUSTOM,
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TIMING_SOURCE_EXPLICIT,
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/* explicitly specified by the display device, more important*/
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TIMING_SOURCE_EDID_CEA_SVD_3D,
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TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
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TIMING_SOURCE_EDID_CEA_SVD_420,
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TIMING_SOURCE_EDID_DETAILED,
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TIMING_SOURCE_EDID_ESTABLISHED,
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TIMING_SOURCE_EDID_STANDARD,
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TIMING_SOURCE_EDID_CEA_SVD,
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TIMING_SOURCE_EDID_CVT_3BYTE,
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TIMING_SOURCE_EDID_4BYTE,
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TIMING_SOURCE_VBIOS,
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TIMING_SOURCE_CV,
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TIMING_SOURCE_TV,
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TIMING_SOURCE_HDMI_VIC,
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/* implicitly specified by display device, still safe but less important*/
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TIMING_SOURCE_DEFAULT,
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/* only used for custom base modes */
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TIMING_SOURCE_CUSTOM_BASE,
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/* these timing might not work, least important*/
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TIMING_SOURCE_RANGELIMIT,
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TIMING_SOURCE_OS_FORCED,
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TIMING_SOURCE_IMPLICIT,
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/* only used by default mode list*/
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TIMING_SOURCE_BASICMODE,
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TIMING_SOURCE_COUNT
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};
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struct stereo_3d_features {
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bool supported ;
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bool allTimings ;
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bool cloneMode ;
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bool scaling ;
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bool singleFrameSWPacked;
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};
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enum dc_timing_support_method {
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TIMING_SUPPORT_METHOD_UNDEFINED,
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TIMING_SUPPORT_METHOD_EXPLICIT,
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TIMING_SUPPORT_METHOD_IMPLICIT,
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TIMING_SUPPORT_METHOD_NATIVE
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};
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struct dc_mode_info {
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uint32_t pixel_width;
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uint32_t pixel_height;
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uint32_t field_rate;
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/* Vertical refresh rate for progressive modes.
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* Field rate for interlaced modes.*/
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enum dc_timing_standard timing_standard;
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enum dc_timing_source timing_source;
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struct dc_mode_flags flags;
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};
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enum dc_power_state {
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DC_POWER_STATE_ON = 1,
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DC_POWER_STATE_STANDBY,
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DC_POWER_STATE_SUSPEND,
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DC_POWER_STATE_OFF
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};
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/* DC PowerStates */
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enum dc_video_power_state {
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DC_VIDEO_POWER_UNSPECIFIED = 0,
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DC_VIDEO_POWER_ON = 1,
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DC_VIDEO_POWER_STANDBY,
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DC_VIDEO_POWER_SUSPEND,
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DC_VIDEO_POWER_OFF,
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DC_VIDEO_POWER_HIBERNATE,
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DC_VIDEO_POWER_SHUTDOWN,
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DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
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DC_VIDEO_POWER_AFTER_RESET,
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DC_VIDEO_POWER_MAXIMUM
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};
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enum dc_acpi_cm_power_state {
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DC_ACPI_CM_POWER_STATE_D0 = 1,
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DC_ACPI_CM_POWER_STATE_D1 = 2,
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DC_ACPI_CM_POWER_STATE_D2 = 4,
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DC_ACPI_CM_POWER_STATE_D3 = 8
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};
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enum dc_connection_type {
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dc_connection_none,
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dc_connection_single,
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dc_connection_mst_branch,
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dc_connection_active_dongle
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};
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struct dc_csc_adjustments {
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struct fixed31_32 contrast;
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struct fixed31_32 saturation;
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struct fixed31_32 brightness;
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struct fixed31_32 hue;
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};
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enum dpcd_downstream_port_max_bpc {
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DOWN_STREAM_MAX_8BPC = 0,
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DOWN_STREAM_MAX_10BPC,
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DOWN_STREAM_MAX_12BPC,
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DOWN_STREAM_MAX_16BPC
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};
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struct dc_dongle_caps {
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/* dongle type (DP converter, CV smart dongle) */
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enum display_dongle_type dongle_type;
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bool extendedCapValid;
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/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
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indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
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bool is_dp_hdmi_s3d_converter;
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bool is_dp_hdmi_ycbcr422_pass_through;
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bool is_dp_hdmi_ycbcr420_pass_through;
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bool is_dp_hdmi_ycbcr422_converter;
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bool is_dp_hdmi_ycbcr420_converter;
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uint32_t dp_hdmi_max_bpc;
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uint32_t dp_hdmi_max_pixel_clk;
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};
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/* Scaling format */
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enum scaling_transformation {
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SCALING_TRANSFORMATION_UNINITIALIZED,
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SCALING_TRANSFORMATION_IDENTITY = 0x0001,
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SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
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SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
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SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
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SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
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SCALING_TRANSFORMATION_INVALID = 0x80000000,
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/* Flag the first and last */
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SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
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SCALING_TRANSFORMATION_END =
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SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
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};
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enum display_content_type {
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DISPLAY_CONTENT_TYPE_NO_DATA = 0,
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DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
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DISPLAY_CONTENT_TYPE_PHOTO = 2,
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DISPLAY_CONTENT_TYPE_CINEMA = 4,
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DISPLAY_CONTENT_TYPE_GAME = 8
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};
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/* audio*/
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union audio_sample_rates {
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struct sample_rates {
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uint8_t RATE_32:1;
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uint8_t RATE_44_1:1;
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uint8_t RATE_48:1;
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uint8_t RATE_88_2:1;
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uint8_t RATE_96:1;
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uint8_t RATE_176_4:1;
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uint8_t RATE_192:1;
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} rate;
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uint8_t all;
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};
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struct audio_speaker_flags {
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uint32_t FL_FR:1;
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uint32_t LFE:1;
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uint32_t FC:1;
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uint32_t RL_RR:1;
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uint32_t RC:1;
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uint32_t FLC_FRC:1;
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uint32_t RLC_RRC:1;
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uint32_t SUPPORT_AI:1;
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};
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struct audio_speaker_info {
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uint32_t ALLSPEAKERS:7;
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uint32_t SUPPORT_AI:1;
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};
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struct audio_info_flags {
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union {
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struct audio_speaker_flags speaker_flags;
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struct audio_speaker_info info;
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uint8_t all;
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};
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};
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enum audio_format_code {
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AUDIO_FORMAT_CODE_FIRST = 1,
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AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
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AUDIO_FORMAT_CODE_AC3,
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/*Layers 1 & 2 */
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AUDIO_FORMAT_CODE_MPEG1,
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/*MPEG1 Layer 3 */
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AUDIO_FORMAT_CODE_MP3,
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/*multichannel */
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AUDIO_FORMAT_CODE_MPEG2,
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AUDIO_FORMAT_CODE_AAC,
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AUDIO_FORMAT_CODE_DTS,
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AUDIO_FORMAT_CODE_ATRAC,
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AUDIO_FORMAT_CODE_1BITAUDIO,
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AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
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AUDIO_FORMAT_CODE_DTS_HD,
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AUDIO_FORMAT_CODE_MAT_MLP,
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AUDIO_FORMAT_CODE_DST,
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AUDIO_FORMAT_CODE_WMAPRO,
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AUDIO_FORMAT_CODE_LAST,
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AUDIO_FORMAT_CODE_COUNT =
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AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
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};
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struct audio_mode {
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/* ucData[0] [6:3] */
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enum audio_format_code format_code;
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/* ucData[0] [2:0] */
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uint8_t channel_count;
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/* ucData[1] */
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union audio_sample_rates sample_rates;
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union {
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/* for LPCM */
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uint8_t sample_size;
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/* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */
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uint8_t max_bit_rate;
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/* for Audio Formats 9-15 */
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uint8_t vendor_specific;
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};
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};
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struct audio_info {
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struct audio_info_flags flags;
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uint32_t video_latency;
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uint32_t audio_latency;
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uint32_t display_index;
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uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
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uint32_t manufacture_id;
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uint32_t product_id;
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/* PortID used for ContainerID when defined */
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uint32_t port_id[2];
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uint32_t mode_count;
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/* this field must be last in this struct */
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struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
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};
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struct vrr_params {
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enum vrr_state state;
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uint32_t window_min;
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uint32_t window_max;
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uint32_t inserted_frame_duration_in_us;
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uint32_t frames_to_insert;
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uint32_t frame_counter;
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};
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struct dc_info_packet {
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bool valid;
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uint8_t hb0;
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uint8_t hb1;
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uint8_t hb2;
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uint8_t hb3;
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uint8_t sb[32];
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};
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#define DC_PLANE_UPDATE_TIMES_MAX 10
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struct dc_plane_flip_time {
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unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
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unsigned int index;
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unsigned int prev_update_time_in_us;
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};
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// Will combine with vrr_params at some point.
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struct freesync_context {
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bool supported;
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bool enabled;
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bool active;
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unsigned int min_refresh_in_micro_hz;
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unsigned int nominal_refresh_in_micro_hz;
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};
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struct psr_config {
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unsigned char psr_version;
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unsigned int psr_rfb_setup_time;
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bool psr_exit_link_training_required;
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bool psr_frame_capture_indication_req;
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unsigned int psr_sdp_transmit_line_num_deadline;
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};
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union dmcu_psr_level {
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struct {
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unsigned int SKIP_CRC:1;
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unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
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unsigned int SKIP_PHY_POWER_DOWN:1;
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unsigned int SKIP_AUX_ACK_CHECK:1;
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unsigned int SKIP_CRTC_DISABLE:1;
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unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
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unsigned int SKIP_SMU_NOTIFICATION:1;
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unsigned int SKIP_AUTO_STATE_ADVANCE:1;
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unsigned int DISABLE_PSR_ENTRY_ABORT:1;
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unsigned int SKIP_SINGLE_OTG_DISABLE:1;
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unsigned int RESERVED:22;
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} bits;
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unsigned int u32all;
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};
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enum physical_phy_id {
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PHYLD_0,
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PHYLD_1,
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PHYLD_2,
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PHYLD_3,
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PHYLD_4,
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PHYLD_5,
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PHYLD_6,
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PHYLD_7,
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PHYLD_8,
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PHYLD_9,
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PHYLD_COUNT,
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PHYLD_UNKNOWN = (-1L)
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};
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enum phy_type {
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PHY_TYPE_UNKNOWN = 1,
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PHY_TYPE_PCIE_PHY = 2,
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PHY_TYPE_UNIPHY = 3,
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};
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struct psr_context {
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/* ddc line */
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enum channel_id channel;
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/* Transmitter id */
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enum transmitter transmitterId;
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/* Engine Id is used for Dig Be source select */
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enum engine_id engineId;
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/* Controller Id used for Dig Fe source select */
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enum controller_id controllerId;
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/* Pcie or Uniphy */
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enum phy_type phyType;
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/* Physical PHY Id used by SMU interpretation */
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enum physical_phy_id smuPhyId;
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/* Vertical total pixels from crtc timing.
|
* This is used for static screen detection.
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* ie. If we want to detect half a frame,
|
* we use this to determine the hyst lines.
|
*/
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unsigned int crtcTimingVerticalTotal;
|
/* PSR supported from panel capabilities and
|
* current display configuration
|
*/
|
bool psrSupportedDisplayConfig;
|
/* Whether fast link training is supported by the panel */
|
bool psrExitLinkTrainingRequired;
|
/* If RFB setup time is greater than the total VBLANK time,
|
* it is not possible for the sink to capture the video frame
|
* in the same frame the SDP is sent. In this case,
|
* the frame capture indication bit should be set and an extra
|
* static frame should be transmitted to the sink.
|
*/
|
bool psrFrameCaptureIndicationReq;
|
/* Set the last possible line SDP may be transmitted without violating
|
* the RFB setup time or entering the active video frame.
|
*/
|
unsigned int sdpTransmitLineNumDeadline;
|
/* The VSync rate in Hz used to calculate the
|
* step size for smooth brightness feature
|
*/
|
unsigned int vsyncRateHz;
|
unsigned int skipPsrWaitForPllLock;
|
unsigned int numberOfControllers;
|
/* Unused, for future use. To indicate that first changed frame from
|
* state3 shouldn't result in psr_inactive, but rather to perform
|
* an automatic single frame rfb_update.
|
*/
|
bool rfb_update_auto_en;
|
/* Number of frame before entering static screen */
|
unsigned int timehyst_frames;
|
/* Partial frames before entering static screen */
|
unsigned int hyst_lines;
|
/* # of repeated AUX transaction attempts to make before
|
* indicating failure to the driver
|
*/
|
unsigned int aux_repeats;
|
/* Controls hw blocks to power down during PSR active state */
|
union dmcu_psr_level psr_level;
|
/* Controls additional delay after remote frame capture before
|
* continuing powerd own
|
*/
|
unsigned int frame_delay;
|
};
|
|
struct colorspace_transform {
|
struct fixed31_32 matrix[12];
|
bool enable_remap;
|
};
|
|
enum i2c_mot_mode {
|
I2C_MOT_UNDEF,
|
I2C_MOT_TRUE,
|
I2C_MOT_FALSE
|
};
|
|
#endif /* DC_TYPES_H_ */
|
