/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DC_HW_TYPES_H
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#define DC_HW_TYPES_H
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#include "os_types.h"
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#include "fixed31_32.h"
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#include "signal_types.h"
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/******************************************************************************
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* Data types for Virtual HW Layer of DAL3.
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* (see DAL3 design documents for HW Layer definition)
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*
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* The intended uses are:
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* 1. Generation pseudocode sequences for HW programming.
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* 2. Implementation of real HW programming by HW Sequencer of DAL3.
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*
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* Note: do *not* add any types which are *not* used for HW programming - this
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* will ensure separation of Logic layer from HW layer.
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******************************************************************************/
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union large_integer {
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struct {
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uint32_t low_part;
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int32_t high_part;
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};
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struct {
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uint32_t low_part;
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int32_t high_part;
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} u;
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int64_t quad_part;
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};
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#define PHYSICAL_ADDRESS_LOC union large_integer
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enum dc_plane_addr_type {
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PLN_ADDR_TYPE_GRAPHICS = 0,
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PLN_ADDR_TYPE_GRPH_STEREO,
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PLN_ADDR_TYPE_VIDEO_PROGRESSIVE,
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};
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struct dc_plane_address {
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enum dc_plane_addr_type type;
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bool tmz_surface;
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union {
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struct{
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PHYSICAL_ADDRESS_LOC addr;
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PHYSICAL_ADDRESS_LOC meta_addr;
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union large_integer dcc_const_color;
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} grph;
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/*stereo*/
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struct {
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PHYSICAL_ADDRESS_LOC left_addr;
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PHYSICAL_ADDRESS_LOC left_meta_addr;
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union large_integer left_dcc_const_color;
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PHYSICAL_ADDRESS_LOC right_addr;
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PHYSICAL_ADDRESS_LOC right_meta_addr;
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union large_integer right_dcc_const_color;
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} grph_stereo;
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/*video progressive*/
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struct {
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PHYSICAL_ADDRESS_LOC luma_addr;
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PHYSICAL_ADDRESS_LOC luma_meta_addr;
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union large_integer luma_dcc_const_color;
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PHYSICAL_ADDRESS_LOC chroma_addr;
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PHYSICAL_ADDRESS_LOC chroma_meta_addr;
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union large_integer chroma_dcc_const_color;
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} video_progressive;
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};
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};
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struct dc_size {
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int width;
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int height;
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};
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struct rect {
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int x;
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int y;
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int width;
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int height;
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};
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union plane_size {
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/* Grph or Video will be selected
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* based on format above:
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* Use Video structure if
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* format >= DalPixelFormat_VideoBegin
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* else use Grph structure
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*/
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struct {
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struct rect surface_size;
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/* Graphic surface pitch in pixels.
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* In LINEAR_GENERAL mode, pitch
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* is 32 pixel aligned.
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*/
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int surface_pitch;
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} grph;
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struct {
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struct rect luma_size;
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/* Graphic surface pitch in pixels.
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* In LINEAR_GENERAL mode, pitch is
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* 32 pixel aligned.
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*/
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int luma_pitch;
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struct rect chroma_size;
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/* Graphic surface pitch in pixels.
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* In LINEAR_GENERAL mode, pitch is
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* 32 pixel aligned.
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*/
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int chroma_pitch;
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} video;
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};
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struct dc_plane_dcc_param {
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bool enable;
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union {
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struct {
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int meta_pitch;
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bool independent_64b_blks;
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} grph;
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struct {
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int meta_pitch_l;
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bool independent_64b_blks_l;
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int meta_pitch_c;
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bool independent_64b_blks_c;
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} video;
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};
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};
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/*Displayable pixel format in fb*/
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enum surface_pixel_format {
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SURFACE_PIXEL_FORMAT_GRPH_BEGIN = 0,
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/*TOBE REMOVED paletta 256 colors*/
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SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS =
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SURFACE_PIXEL_FORMAT_GRPH_BEGIN,
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/*16 bpp*/
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SURFACE_PIXEL_FORMAT_GRPH_ARGB1555,
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/*16 bpp*/
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SURFACE_PIXEL_FORMAT_GRPH_RGB565,
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/*32 bpp*/
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SURFACE_PIXEL_FORMAT_GRPH_ARGB8888,
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/*32 bpp swaped*/
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SURFACE_PIXEL_FORMAT_GRPH_ABGR8888,
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SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010,
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/*swaped*/
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SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010,
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/*TOBE REMOVED swaped, XR_BIAS has no differance
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* for pixel layout than previous and we can
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* delete this after discusion*/
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SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS,
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/*64 bpp */
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SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616,
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/*float*/
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SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F,
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/*swaped & float*/
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SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
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/*grow graphics here if necessary */
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SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888,
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
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SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
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SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
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SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
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SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
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SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
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SURFACE_PIXEL_FORMAT_INVALID
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/*grow 444 video here if necessary */
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};
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/* Pixel format */
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enum pixel_format {
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/*graph*/
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PIXEL_FORMAT_UNINITIALIZED,
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PIXEL_FORMAT_INDEX8,
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PIXEL_FORMAT_RGB565,
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PIXEL_FORMAT_ARGB8888,
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PIXEL_FORMAT_ARGB2101010,
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PIXEL_FORMAT_ARGB2101010_XRBIAS,
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PIXEL_FORMAT_FP16,
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/*video*/
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PIXEL_FORMAT_420BPP8,
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PIXEL_FORMAT_420BPP10,
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/*end of pixel format definition*/
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PIXEL_FORMAT_INVALID,
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PIXEL_FORMAT_GRPH_BEGIN = PIXEL_FORMAT_INDEX8,
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PIXEL_FORMAT_GRPH_END = PIXEL_FORMAT_FP16,
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PIXEL_FORMAT_VIDEO_BEGIN = PIXEL_FORMAT_420BPP8,
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PIXEL_FORMAT_VIDEO_END = PIXEL_FORMAT_420BPP10,
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PIXEL_FORMAT_UNKNOWN
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};
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enum tile_split_values {
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DC_DISPLAY_MICRO_TILING = 0x0,
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DC_THIN_MICRO_TILING = 0x1,
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DC_DEPTH_MICRO_TILING = 0x2,
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DC_ROTATED_MICRO_TILING = 0x3,
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};
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/* TODO: These values come from hardware spec. We need to readdress this
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* if they ever change.
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*/
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enum array_mode_values {
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DC_ARRAY_LINEAR_GENERAL = 0,
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DC_ARRAY_LINEAR_ALLIGNED,
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DC_ARRAY_1D_TILED_THIN1,
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DC_ARRAY_1D_TILED_THICK,
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DC_ARRAY_2D_TILED_THIN1,
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DC_ARRAY_PRT_TILED_THIN1,
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DC_ARRAY_PRT_2D_TILED_THIN1,
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DC_ARRAY_2D_TILED_THICK,
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DC_ARRAY_2D_TILED_X_THICK,
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DC_ARRAY_PRT_TILED_THICK,
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DC_ARRAY_PRT_2D_TILED_THICK,
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DC_ARRAY_PRT_3D_TILED_THIN1,
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DC_ARRAY_3D_TILED_THIN1,
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DC_ARRAY_3D_TILED_THICK,
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DC_ARRAY_3D_TILED_X_THICK,
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DC_ARRAY_PRT_3D_TILED_THICK,
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};
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enum tile_mode_values {
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DC_ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
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DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
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};
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enum swizzle_mode_values {
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DC_SW_LINEAR = 0,
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DC_SW_256B_S = 1,
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DC_SW_256_D = 2,
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DC_SW_256_R = 3,
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DC_SW_4KB_S = 5,
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DC_SW_4KB_D = 6,
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DC_SW_4KB_R = 7,
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DC_SW_64KB_S = 9,
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DC_SW_64KB_D = 10,
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DC_SW_64KB_R = 11,
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DC_SW_VAR_S = 13,
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DC_SW_VAR_D = 14,
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DC_SW_VAR_R = 15,
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DC_SW_64KB_S_T = 17,
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DC_SW_64KB_D_T = 18,
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DC_SW_4KB_S_X = 21,
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DC_SW_4KB_D_X = 22,
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DC_SW_4KB_R_X = 23,
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DC_SW_64KB_S_X = 25,
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DC_SW_64KB_D_X = 26,
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DC_SW_64KB_R_X = 27,
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DC_SW_VAR_S_X = 29,
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DC_SW_VAR_D_X = 30,
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DC_SW_VAR_R_X = 31,
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DC_SW_MAX
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};
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union dc_tiling_info {
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struct {
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/* Specifies the number of memory banks for tiling
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* purposes.
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* Only applies to 2D and 3D tiling modes.
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* POSSIBLE VALUES: 2,4,8,16
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*/
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unsigned int num_banks;
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/* Specifies the number of tiles in the x direction
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* to be incorporated into the same bank.
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* Only applies to 2D and 3D tiling modes.
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* POSSIBLE VALUES: 1,2,4,8
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*/
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unsigned int bank_width;
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unsigned int bank_width_c;
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/* Specifies the number of tiles in the y direction to
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* be incorporated into the same bank.
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* Only applies to 2D and 3D tiling modes.
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* POSSIBLE VALUES: 1,2,4,8
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*/
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unsigned int bank_height;
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unsigned int bank_height_c;
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/* Specifies the macro tile aspect ratio. Only applies
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* to 2D and 3D tiling modes.
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*/
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unsigned int tile_aspect;
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unsigned int tile_aspect_c;
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/* Specifies the number of bytes that will be stored
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* contiguously for each tile.
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* If the tile data requires more storage than this
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* amount, it is split into multiple slices.
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* This field must not be larger than
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* GB_ADDR_CONFIG.DRAM_ROW_SIZE.
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* Only applies to 2D and 3D tiling modes.
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* For color render targets, TILE_SPLIT >= 256B.
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*/
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enum tile_split_values tile_split;
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enum tile_split_values tile_split_c;
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/* Specifies the addressing within a tile.
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* 0x0 - DISPLAY_MICRO_TILING
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* 0x1 - THIN_MICRO_TILING
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* 0x2 - DEPTH_MICRO_TILING
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* 0x3 - ROTATED_MICRO_TILING
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*/
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enum tile_mode_values tile_mode;
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enum tile_mode_values tile_mode_c;
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/* Specifies the number of pipes and how they are
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* interleaved in the surface.
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* Refer to memory addressing document for complete
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* details and constraints.
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*/
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unsigned int pipe_config;
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/* Specifies the tiling mode of the surface.
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* THIN tiles use an 8x8x1 tile size.
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* THICK tiles use an 8x8x4 tile size.
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* 2D tiling modes rotate banks for successive Z slices
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* 3D tiling modes rotate pipes and banks for Z slices
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* Refer to memory addressing document for complete
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* details and constraints.
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*/
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enum array_mode_values array_mode;
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} gfx8;
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struct {
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unsigned int num_pipes;
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unsigned int num_banks;
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unsigned int pipe_interleave;
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unsigned int num_shader_engines;
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unsigned int num_rb_per_se;
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unsigned int max_compressed_frags;
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bool shaderEnable;
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enum swizzle_mode_values swizzle;
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bool meta_linear;
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bool rb_aligned;
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bool pipe_aligned;
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} gfx9;
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};
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/* Rotation angle */
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enum dc_rotation_angle {
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ROTATION_ANGLE_0 = 0,
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ROTATION_ANGLE_90,
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ROTATION_ANGLE_180,
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ROTATION_ANGLE_270,
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ROTATION_ANGLE_COUNT
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};
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enum dc_scan_direction {
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SCAN_DIRECTION_UNKNOWN = 0,
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SCAN_DIRECTION_HORIZONTAL = 1, /* 0, 180 rotation */
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SCAN_DIRECTION_VERTICAL = 2, /* 90, 270 rotation */
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};
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struct dc_cursor_position {
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uint32_t x;
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uint32_t y;
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uint32_t x_hotspot;
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uint32_t y_hotspot;
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/*
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* This parameter indicates whether HW cursor should be enabled
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*/
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bool enable;
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};
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struct dc_cursor_mi_param {
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unsigned int pixel_clk_khz;
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unsigned int ref_clk_khz;
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struct rect viewport;
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struct fixed31_32 h_scale_ratio;
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struct fixed31_32 v_scale_ratio;
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enum dc_rotation_angle rotation;
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bool mirror;
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};
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/* IPP related types */
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enum {
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GAMMA_RGB_256_ENTRIES = 256,
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GAMMA_RGB_FLOAT_1024_ENTRIES = 1024,
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GAMMA_CS_TFM_1D_ENTRIES = 4096,
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GAMMA_CUSTOM_ENTRIES = 4096,
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GAMMA_MAX_ENTRIES = 4096
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};
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enum dc_gamma_type {
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GAMMA_RGB_256 = 1,
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GAMMA_RGB_FLOAT_1024 = 2,
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GAMMA_CS_TFM_1D = 3,
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GAMMA_CUSTOM = 4,
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};
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struct dc_csc_transform {
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uint16_t matrix[12];
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bool enable_adjustment;
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};
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struct dc_gamma {
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struct kref refcount;
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enum dc_gamma_type type;
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unsigned int num_entries;
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struct dc_gamma_entries {
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struct fixed31_32 red[GAMMA_MAX_ENTRIES];
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struct fixed31_32 green[GAMMA_MAX_ENTRIES];
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struct fixed31_32 blue[GAMMA_MAX_ENTRIES];
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} entries;
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/* private to DC core */
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struct dc_context *ctx;
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bool is_identity;
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};
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/* Used by both ipp amd opp functions*/
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/* TODO: to be consolidated with enum color_space */
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/*
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* This enum is for programming CURSOR_MODE register field. What this register
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* should be programmed to depends on OS requested cursor shape flags and what
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* we stored in the cursor surface.
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*/
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enum dc_cursor_color_format {
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CURSOR_MODE_MONO,
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CURSOR_MODE_COLOR_1BIT_AND,
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CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
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CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
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};
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/*
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* This is all the parameters required by DAL in order to update the cursor
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* attributes, including the new cursor image surface address, size, hotspot
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* location, color format, etc.
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*/
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union dc_cursor_attribute_flags {
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struct {
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uint32_t ENABLE_MAGNIFICATION:1;
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uint32_t INVERSE_TRANSPARENT_CLAMPING:1;
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uint32_t HORIZONTAL_MIRROR:1;
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uint32_t VERTICAL_MIRROR:1;
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uint32_t INVERT_PIXEL_DATA:1;
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uint32_t ZERO_EXPANSION:1;
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uint32_t MIN_MAX_INVERT:1;
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uint32_t RESERVED:25;
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} bits;
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uint32_t value;
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};
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struct dc_cursor_attributes {
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PHYSICAL_ADDRESS_LOC address;
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uint32_t pitch;
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/* Width and height should correspond to cursor surface width x heigh */
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uint32_t width;
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uint32_t height;
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enum dc_cursor_color_format color_format;
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uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
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/* In case we support HW Cursor rotation in the future */
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enum dc_rotation_angle rotation_angle;
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union dc_cursor_attribute_flags attribute_flags;
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};
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struct dpp_cursor_attributes {
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int bias;
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int scale;
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};
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/* OPP */
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enum dc_color_space {
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COLOR_SPACE_UNKNOWN,
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COLOR_SPACE_SRGB,
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COLOR_SPACE_XR_RGB,
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COLOR_SPACE_SRGB_LIMITED,
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COLOR_SPACE_MSREF_SCRGB,
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COLOR_SPACE_YCBCR601,
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COLOR_SPACE_YCBCR709,
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COLOR_SPACE_XV_YCC_709,
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COLOR_SPACE_XV_YCC_601,
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COLOR_SPACE_YCBCR601_LIMITED,
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COLOR_SPACE_YCBCR709_LIMITED,
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COLOR_SPACE_2020_RGB_FULLRANGE,
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COLOR_SPACE_2020_RGB_LIMITEDRANGE,
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COLOR_SPACE_2020_YCBCR,
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COLOR_SPACE_ADOBERGB,
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COLOR_SPACE_DCIP3,
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COLOR_SPACE_DISPLAYNATIVE,
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COLOR_SPACE_DOLBYVISION,
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COLOR_SPACE_APPCTRL,
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COLOR_SPACE_CUSTOMPOINTS,
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};
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enum dc_dither_option {
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DITHER_OPTION_DEFAULT,
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DITHER_OPTION_DISABLE,
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DITHER_OPTION_FM6,
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DITHER_OPTION_FM8,
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DITHER_OPTION_FM10,
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DITHER_OPTION_SPATIAL6_FRAME_RANDOM,
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DITHER_OPTION_SPATIAL8_FRAME_RANDOM,
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DITHER_OPTION_SPATIAL10_FRAME_RANDOM,
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DITHER_OPTION_SPATIAL6,
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DITHER_OPTION_SPATIAL8,
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DITHER_OPTION_SPATIAL10,
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DITHER_OPTION_TRUN6,
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DITHER_OPTION_TRUN8,
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DITHER_OPTION_TRUN10,
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DITHER_OPTION_TRUN10_SPATIAL8,
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DITHER_OPTION_TRUN10_SPATIAL6,
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DITHER_OPTION_TRUN10_FM8,
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DITHER_OPTION_TRUN10_FM6,
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DITHER_OPTION_TRUN10_SPATIAL8_FM6,
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DITHER_OPTION_SPATIAL10_FM8,
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DITHER_OPTION_SPATIAL10_FM6,
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DITHER_OPTION_TRUN8_SPATIAL6,
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DITHER_OPTION_TRUN8_FM6,
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DITHER_OPTION_SPATIAL8_FM6,
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DITHER_OPTION_MAX = DITHER_OPTION_SPATIAL8_FM6,
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DITHER_OPTION_INVALID
|
};
|
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enum dc_quantization_range {
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QUANTIZATION_RANGE_UNKNOWN,
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QUANTIZATION_RANGE_FULL,
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QUANTIZATION_RANGE_LIMITED
|
};
|
|
/* XFM */
|
|
/* used in struct dc_plane_state */
|
struct scaling_taps {
|
uint32_t v_taps;
|
uint32_t h_taps;
|
uint32_t v_taps_c;
|
uint32_t h_taps_c;
|
};
|
|
enum dc_timing_standard {
|
DC_TIMING_STANDARD_UNDEFINED,
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DC_TIMING_STANDARD_DMT,
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DC_TIMING_STANDARD_GTF,
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DC_TIMING_STANDARD_CVT,
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DC_TIMING_STANDARD_CVT_RB,
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DC_TIMING_STANDARD_CEA770,
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DC_TIMING_STANDARD_CEA861,
|
DC_TIMING_STANDARD_HDMI,
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DC_TIMING_STANDARD_TV_NTSC,
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DC_TIMING_STANDARD_TV_NTSC_J,
|
DC_TIMING_STANDARD_TV_PAL,
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DC_TIMING_STANDARD_TV_PAL_M,
|
DC_TIMING_STANDARD_TV_PAL_CN,
|
DC_TIMING_STANDARD_TV_SECAM,
|
DC_TIMING_STANDARD_EXPLICIT,
|
/*!< For explicit timings from EDID, VBIOS, etc.*/
|
DC_TIMING_STANDARD_USER_OVERRIDE,
|
/*!< For mode timing override by user*/
|
DC_TIMING_STANDARD_MAX
|
};
|
|
enum dc_color_depth {
|
COLOR_DEPTH_UNDEFINED,
|
COLOR_DEPTH_666,
|
COLOR_DEPTH_888,
|
COLOR_DEPTH_101010,
|
COLOR_DEPTH_121212,
|
COLOR_DEPTH_141414,
|
COLOR_DEPTH_161616,
|
COLOR_DEPTH_COUNT
|
};
|
|
enum dc_pixel_encoding {
|
PIXEL_ENCODING_UNDEFINED,
|
PIXEL_ENCODING_RGB,
|
PIXEL_ENCODING_YCBCR422,
|
PIXEL_ENCODING_YCBCR444,
|
PIXEL_ENCODING_YCBCR420,
|
PIXEL_ENCODING_COUNT
|
};
|
|
enum dc_aspect_ratio {
|
ASPECT_RATIO_NO_DATA,
|
ASPECT_RATIO_4_3,
|
ASPECT_RATIO_16_9,
|
ASPECT_RATIO_64_27,
|
ASPECT_RATIO_256_135,
|
ASPECT_RATIO_FUTURE
|
};
|
|
enum scanning_type {
|
SCANNING_TYPE_NODATA = 0,
|
SCANNING_TYPE_OVERSCAN,
|
SCANNING_TYPE_UNDERSCAN,
|
SCANNING_TYPE_FUTURE,
|
SCANNING_TYPE_UNDEFINED
|
};
|
|
struct dc_crtc_timing_flags {
|
uint32_t INTERLACE :1;
|
uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,
|
it is positive polarity --reversed with dal1 or video bios define*/
|
uint32_t VSYNC_POSITIVE_POLARITY :1; /* when set to 1,
|
it is positive polarity --reversed with dal1 or video bios define*/
|
|
uint32_t HORZ_COUNT_BY_TWO:1;
|
|
uint32_t EXCLUSIVE_3D :1; /* if this bit set,
|
timing can be driven in 3D format only
|
and there is no corresponding 2D timing*/
|
uint32_t RIGHT_EYE_3D_POLARITY :1; /* 1 - means right eye polarity
|
(right eye = '1', left eye = '0') */
|
uint32_t SUB_SAMPLE_3D :1; /* 1 - means left/right images subsampled
|
when mixed into 3D image. 0 - means summation (3D timing is doubled)*/
|
uint32_t USE_IN_3D_VIEW_ONLY :1; /* Do not use this timing in 2D View,
|
because corresponding 2D timing also present in the list*/
|
uint32_t STEREO_3D_PREFERENCE :1; /* Means this is 2D timing
|
and we want to match priority of corresponding 3D timing*/
|
uint32_t Y_ONLY :1;
|
|
uint32_t YCBCR420 :1; /* TODO: shouldn't need this flag, should be a separate pixel format */
|
uint32_t DTD_COUNTER :5; /* values 1 to 16 */
|
|
uint32_t FORCE_HDR :1;
|
|
/* HDMI 2.0 - Support scrambling for TMDS character
|
* rates less than or equal to 340Mcsc */
|
uint32_t LTE_340MCSC_SCRAMBLE:1;
|
|
};
|
|
enum dc_timing_3d_format {
|
TIMING_3D_FORMAT_NONE,
|
TIMING_3D_FORMAT_FRAME_ALTERNATE, /* No stereosync at all*/
|
TIMING_3D_FORMAT_INBAND_FA, /* Inband Frame Alternate (DVI/DP)*/
|
TIMING_3D_FORMAT_DP_HDMI_INBAND_FA, /* Inband FA to HDMI Frame Pack*/
|
/* for active DP-HDMI dongle*/
|
TIMING_3D_FORMAT_SIDEBAND_FA, /* Sideband Frame Alternate (eDP)*/
|
TIMING_3D_FORMAT_HW_FRAME_PACKING,
|
TIMING_3D_FORMAT_SW_FRAME_PACKING,
|
TIMING_3D_FORMAT_ROW_INTERLEAVE,
|
TIMING_3D_FORMAT_COLUMN_INTERLEAVE,
|
TIMING_3D_FORMAT_PIXEL_INTERLEAVE,
|
TIMING_3D_FORMAT_SIDE_BY_SIDE,
|
TIMING_3D_FORMAT_TOP_AND_BOTTOM,
|
TIMING_3D_FORMAT_SBS_SW_PACKED,
|
/* Side-by-side, packed by application/driver into 2D frame*/
|
TIMING_3D_FORMAT_TB_SW_PACKED,
|
/* Top-and-bottom, packed by application/driver into 2D frame*/
|
|
TIMING_3D_FORMAT_MAX,
|
};
|
|
enum trigger_delay {
|
TRIGGER_DELAY_NEXT_PIXEL = 0,
|
TRIGGER_DELAY_NEXT_LINE,
|
};
|
|
enum crtc_event {
|
CRTC_EVENT_VSYNC_RISING = 0,
|
CRTC_EVENT_VSYNC_FALLING
|
};
|
|
struct crtc_trigger_info {
|
bool enabled;
|
struct dc_stream_state *event_source;
|
enum crtc_event event;
|
enum trigger_delay delay;
|
};
|
|
enum vrr_state {
|
VRR_STATE_OFF = 0,
|
VRR_STATE_VARIABLE,
|
VRR_STATE_FIXED,
|
};
|
|
struct dc_crtc_timing_adjust {
|
uint32_t v_total_min;
|
uint32_t v_total_max;
|
};
|
|
struct dc_crtc_timing {
|
uint32_t h_total;
|
uint32_t h_border_left;
|
uint32_t h_addressable;
|
uint32_t h_border_right;
|
uint32_t h_front_porch;
|
uint32_t h_sync_width;
|
|
uint32_t v_total;
|
uint32_t v_border_top;
|
uint32_t v_addressable;
|
uint32_t v_border_bottom;
|
uint32_t v_front_porch;
|
uint32_t v_sync_width;
|
|
uint32_t pix_clk_khz;
|
|
uint32_t vic;
|
uint32_t hdmi_vic;
|
enum dc_timing_3d_format timing_3d_format;
|
enum dc_color_depth display_color_depth;
|
enum dc_pixel_encoding pixel_encoding;
|
enum dc_aspect_ratio aspect_ratio;
|
enum scanning_type scan_type;
|
|
struct dc_crtc_timing_flags flags;
|
};
|
|
#define MAX_TG_COLOR_VALUE 0x3FF
|
struct tg_color {
|
/* Maximum 10 bits color value */
|
uint16_t color_r_cr;
|
uint16_t color_g_y;
|
uint16_t color_b_cb;
|
};
|
|
#endif /* DC_HW_TYPES_H */
|
