// SPDX-License-Identifier: MIT
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/*
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* clock framework for AMD Stoney based clocks
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*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_data/clk-st.h>
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#include <linux/platform_device.h>
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/* Clock Driving Strength 2 register */
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#define CLKDRVSTR2 0x28
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/* Clock Control 1 register */
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#define MISCCLKCNTL1 0x40
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/* Auxiliary clock1 enable bit */
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#define OSCCLKENB 2
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/* 25Mhz auxiliary output clock freq bit */
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#define OSCOUT1CLK25MHZ 16
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#define ST_CLK_48M 0
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#define ST_CLK_25M 1
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#define ST_CLK_MUX 2
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#define ST_CLK_GATE 3
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#define ST_MAX_CLKS 4
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static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
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static struct clk_hw *hws[ST_MAX_CLKS];
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static int st_clk_probe(struct platform_device *pdev)
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{
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struct st_clk_data *st_data;
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st_data = dev_get_platdata(&pdev->dev);
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if (!st_data || !st_data->base)
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return -EINVAL;
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hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
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48000000);
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hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
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25000000);
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hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
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clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
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0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
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clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
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hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
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0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
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CLK_GATE_SET_TO_DISABLE, NULL);
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clk_hw_register_clkdev(hws[ST_CLK_GATE], "oscout1", NULL);
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return 0;
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}
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static int st_clk_remove(struct platform_device *pdev)
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{
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int i;
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for (i = 0; i < ST_MAX_CLKS; i++)
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clk_hw_unregister(hws[i]);
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return 0;
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}
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static struct platform_driver st_clk_driver = {
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.driver = {
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.name = "clk-st",
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.suppress_bind_attrs = true,
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},
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.probe = st_clk_probe,
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.remove = st_clk_remove,
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};
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builtin_platform_driver(st_clk_driver);
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