/*
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* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "clk-regmap.h"
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#define PLLCON_OFFSET(x) (x * 4)
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#define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
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#define PLL_BYPASS_MASK BIT(15)
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#define PLL_BYPASS_SHIFT 15
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#define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
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#define PLL_POSTDIV1_MASK GENMASK(14, 12)
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#define PLL_POSTDIV1_SHIFT 12
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#define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
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#define PLL_FBDIV_MASK GENMASK(11, 0)
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#define PLL_FBDIV_SHIFT 0
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#define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
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#define PLL_POSTDIV2_MASK GENMASK(8, 6)
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#define PLL_POSTDIV2_SHIFT 6
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#define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
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#define PLL_REFDIV_MASK GENMASK(5, 0)
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#define PLL_REFDIV_SHIFT 0
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#define PLL_FOUT_4PHASE_CLK_POWER_DOWN BIT(27)
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#define PLL_FOUT_VCO_CLK_POWER_DOWN BIT(26)
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#define PLL_FOUT_POST_DIV_POWER_DOWN BIT(25)
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#define PLL_DAC_POWER_DOWN BIT(24)
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#define PLL_FRAC(x) UPDATE(x, 23, 0)
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#define PLL_FRAC_MASK GENMASK(23, 0)
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#define PLL_FRAC_SHIFT 0
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#define MIN_FREF_RATE 10000000UL
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#define MAX_FREF_RATE 800000000UL
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#define MIN_FREFDIV_RATE 1000000UL
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#define MAX_FREFDIV_RATE 40000000UL
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#define MIN_FVCO_RATE 400000000UL
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#define MAX_FVCO_RATE 1600000000UL
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#define MIN_FOUTPOSTDIV_RATE 8000000UL
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#define MAX_FOUTPOSTDIV_RATE 1600000000UL
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struct clk_regmap_pll {
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struct clk_hw hw;
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struct device *dev;
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struct regmap *regmap;
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unsigned int reg;
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u8 pd_shift;
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u8 dsmpd_shift;
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u8 lock_shift;
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};
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#define to_clk_regmap_pll(_hw) container_of(_hw, struct clk_regmap_pll, hw)
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static unsigned long
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clk_regmap_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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unsigned int postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass;
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unsigned int con0, con1, con2;
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u64 foutvco, foutpostdiv;
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regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(0), &con0);
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regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1);
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regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(2), &con2);
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bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT;
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postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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dsmpd = (con1 & BIT(pll->dsmpd_shift)) >> pll->dsmpd_shift;
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postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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frac = (con2 & PLL_FRAC_MASK) >> PLL_FRAC_SHIFT;
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if (bypass)
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return prate;
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foutvco = prate * fbdiv;
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do_div(foutvco, refdiv);
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if (!dsmpd) {
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u64 frac_rate = (u64)prate * frac;
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do_div(frac_rate, refdiv);
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foutvco += frac_rate >> 24;
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}
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foutpostdiv = foutvco;
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do_div(foutpostdiv, postdiv1);
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do_div(foutpostdiv, postdiv2);
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return foutpostdiv;
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}
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static long clk_pll_round_rate(unsigned long fin, unsigned long fout,
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u8 *refdiv, u16 *fbdiv,
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u8 *postdiv1, u8 *postdiv2,
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u32 *frac, u8 *dsmpd, u8 *bypass)
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{
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u8 min_refdiv, max_refdiv, postdiv;
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u8 _dsmpd = 1, _postdiv1 = 0, _postdiv2 = 0, _refdiv = 0;
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u16 _fbdiv = 0;
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u32 _frac = 0;
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u64 foutvco, foutpostdiv;
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/*
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* FREF : 10MHz ~ 800MHz
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* FREFDIV : 1MHz ~ 40MHz
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* FOUTVCO : 400MHz ~ 1.6GHz
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* FOUTPOSTDIV : 8MHz ~ 1.6GHz
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*/
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if (fin < MIN_FREF_RATE || fin > MAX_FREF_RATE)
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return -EINVAL;
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if (fout < MIN_FOUTPOSTDIV_RATE || fout > MAX_FOUTPOSTDIV_RATE)
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return -EINVAL;
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if (fin == fout) {
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if (bypass)
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*bypass = true;
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return fin;
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}
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min_refdiv = DIV_ROUND_UP(fin, MAX_FREFDIV_RATE);
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max_refdiv = fin / MIN_FREFDIV_RATE;
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if (max_refdiv > 64)
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max_refdiv = 64;
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if (fout < MIN_FVCO_RATE) {
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postdiv = DIV_ROUND_UP_ULL(MIN_FVCO_RATE, fout);
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for (_postdiv2 = 1; _postdiv2 < 8; _postdiv2++) {
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if (postdiv % _postdiv2)
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continue;
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_postdiv1 = postdiv / _postdiv2;
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if (_postdiv1 > 0 && _postdiv1 < 8)
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break;
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}
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if (_postdiv2 > 7)
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return -EINVAL;
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fout *= _postdiv1 * _postdiv2;
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} else {
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_postdiv1 = 1;
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_postdiv2 = 1;
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}
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for (_refdiv = min_refdiv; _refdiv <= max_refdiv; _refdiv++) {
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u64 tmp, frac_rate;
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if (fin % _refdiv)
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continue;
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tmp = (u64)fout * _refdiv;
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do_div(tmp, fin);
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_fbdiv = tmp;
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if (_fbdiv < 10 || _fbdiv > 1600)
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continue;
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tmp = (u64)_fbdiv * fin;
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do_div(tmp, _refdiv);
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if (fout < MIN_FVCO_RATE || fout > MAX_FVCO_RATE)
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continue;
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frac_rate = fout - tmp;
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if (frac_rate) {
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tmp = (u64)frac_rate * _refdiv;
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tmp <<= 24;
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do_div(tmp, fin);
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_frac = tmp;
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_dsmpd = 0;
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}
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break;
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}
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/*
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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*
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* If DSMPD = 0 (DSM is enabled, "fractional mode")
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* FOUTVCO = FREF / REFDIV * (FBDIV + FRAC / 2^24)
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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*/
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foutvco = fin * _fbdiv;
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do_div(foutvco, _refdiv);
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if (!_dsmpd) {
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u64 frac_rate = (u64)fin * _frac;
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do_div(frac_rate, _refdiv);
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foutvco += frac_rate >> 24;
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}
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foutpostdiv = foutvco;
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do_div(foutpostdiv, _postdiv1);
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do_div(foutpostdiv, _postdiv2);
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if (refdiv)
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*refdiv = _refdiv;
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if (fbdiv)
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*fbdiv = _fbdiv;
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if (postdiv1)
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*postdiv1 = _postdiv1;
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if (postdiv2)
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*postdiv2 = _postdiv2;
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if (frac)
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*frac = _frac;
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if (dsmpd)
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*dsmpd = _dsmpd;
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if (bypass)
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*bypass = false;
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return (unsigned long)foutpostdiv;
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}
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static long
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clk_regmap_pll_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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long rate;
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rate = clk_pll_round_rate(*prate, drate, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL);
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dev_dbg(pll->dev, "%s: prate=%ld, drate=%ld, rate=%ld\n",
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clk_hw_get_name(hw), *prate, drate, rate);
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return rate;
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}
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static int
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clk_regmap_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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u8 refdiv, postdiv1, postdiv2, dsmpd, bypass;
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u16 fbdiv;
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u32 frac;
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long rate;
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rate = clk_pll_round_rate(prate, drate, &refdiv, &fbdiv, &postdiv1,
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&postdiv2, &frac, &dsmpd, &bypass);
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if (rate < 0)
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return rate;
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dev_dbg(pll->dev, "%s: rate=%ld, bypass=%d\n",
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clk_hw_get_name(hw), drate, bypass);
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if (bypass) {
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(0),
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PLL_BYPASS(1));
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} else {
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(0),
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PLL_BYPASS(0) | PLL_POSTDIV1(postdiv1) |
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PLL_FBDIV(fbdiv));
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),
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HIWORD_UPDATE(dsmpd, pll->dsmpd_shift, pll->dsmpd_shift) |
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PLL_POSTDIV2(postdiv2) | PLL_REFDIV(refdiv));
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(2),
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PLL_FRAC(frac));
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dev_dbg(pll->dev, "refdiv=%d, fbdiv=%d, frac=%d\n",
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refdiv, fbdiv, frac);
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dev_dbg(pll->dev, "postdiv1=%d, postdiv2=%d\n",
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postdiv1, postdiv2);
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}
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return 0;
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}
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static int clk_regmap_pll_prepare(struct clk_hw *hw)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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u32 v;
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int ret;
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),
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HIWORD_UPDATE(0, pll->pd_shift, pll->pd_shift));
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ret = regmap_read_poll_timeout(pll->regmap,
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pll->reg + PLLCON_OFFSET(1),
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v, v & BIT(pll->lock_shift), 50, 50000);
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if (ret)
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dev_err(pll->dev, "%s is not lock\n", clk_hw_get_name(hw));
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return 0;
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}
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static void clk_regmap_pll_unprepare(struct clk_hw *hw)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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regmap_write(pll->regmap, pll->reg + PLLCON_OFFSET(1),
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HIWORD_UPDATE(1, pll->pd_shift, pll->pd_shift));
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}
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static int clk_regmap_pll_is_prepared(struct clk_hw *hw)
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{
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struct clk_regmap_pll *pll = to_clk_regmap_pll(hw);
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unsigned int con1;
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regmap_read(pll->regmap, pll->reg + PLLCON_OFFSET(1), &con1);
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return !(con1 & BIT(pll->pd_shift));
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}
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static const struct clk_ops clk_regmap_pll_ops = {
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.recalc_rate = clk_regmap_pll_recalc_rate,
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.round_rate = clk_regmap_pll_round_rate,
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.set_rate = clk_regmap_pll_set_rate,
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.prepare = clk_regmap_pll_prepare,
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.unprepare = clk_regmap_pll_unprepare,
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.is_prepared = clk_regmap_pll_is_prepared,
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};
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struct clk *
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devm_clk_regmap_register_pll(struct device *dev, const char *name,
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const char *parent_name,
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struct regmap *regmap, u32 reg, u8 pd_shift,
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u8 dsmpd_shift, u8 lock_shift,
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unsigned long flags)
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{
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struct clk_regmap_pll *pll;
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struct clk_init_data init = {};
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pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_regmap_pll_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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pll->dev = dev;
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pll->regmap = regmap;
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pll->reg = reg;
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pll->pd_shift = pd_shift;
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pll->dsmpd_shift = dsmpd_shift;
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pll->lock_shift = lock_shift;
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pll->hw.init = &init;
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return devm_clk_register(dev, &pll->hw);
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}
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EXPORT_SYMBOL_GPL(devm_clk_regmap_register_pll);
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