// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "clk.h"
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DEFINE_SPINLOCK(imx_ccm_lock);
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void __init imx_check_clocks(struct clk *clks[], unsigned int count)
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{
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unsigned i;
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for (i = 0; i < count; i++)
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if (IS_ERR(clks[i]))
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pr_err("i.MX clk %u: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
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{
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struct of_phandle_args phandle;
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struct clk *clk = ERR_PTR(-ENODEV);
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char *path;
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path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
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if (!path)
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return ERR_PTR(-ENOMEM);
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phandle.np = of_find_node_by_path(path);
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kfree(path);
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if (phandle.np) {
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clk = of_clk_get_from_provider(&phandle);
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of_node_put(phandle.np);
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}
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return clk;
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}
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struct clk * __init imx_obtain_fixed_clock(
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const char *name, unsigned long rate)
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{
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struct clk *clk;
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clk = imx_obtain_fixed_clock_from_dt(name);
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if (IS_ERR(clk))
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clk = imx_clk_fixed(name, rate);
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return clk;
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}
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/*
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* This fixups the register CCM_CSCMR1 write value.
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* The write/read/divider values of the aclk_podf field
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* of that register have the relationship described by
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* the following table:
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*
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* write value read value divider
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* 3b'000 3b'110 7
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* 3b'001 3b'111 8
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* 3b'010 3b'100 5
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* 3b'011 3b'101 6
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* 3b'100 3b'010 3
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* 3b'101 3b'011 4
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* 3b'110 3b'000 1
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* 3b'111 3b'001 2(default)
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*
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* That's why we do the xor operation below.
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*/
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#define CSCMR1_FIXUP 0x00600000
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void imx_cscmr1_fixup(u32 *val)
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{
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*val ^= CSCMR1_FIXUP;
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return;
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}
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static int imx_keep_uart_clocks __initdata;
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static struct clk ** const *imx_uart_clocks __initdata;
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static int __init imx_keep_uart_clocks_param(char *str)
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{
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imx_keep_uart_clocks = 1;
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return 0;
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}
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__setup_param("earlycon", imx_keep_uart_earlycon,
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imx_keep_uart_clocks_param, 0);
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__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
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imx_keep_uart_clocks_param, 0);
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void __init imx_register_uart_clocks(struct clk ** const clks[])
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{
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if (imx_keep_uart_clocks) {
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int i;
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imx_uart_clocks = clks;
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for (i = 0; imx_uart_clocks[i]; i++)
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clk_prepare_enable(*imx_uart_clocks[i]);
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}
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}
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static int __init imx_clk_disable_uart(void)
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{
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if (imx_keep_uart_clocks && imx_uart_clocks) {
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int i;
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for (i = 0; imx_uart_clocks[i]; i++)
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clk_disable_unprepare(*imx_uart_clocks[i]);
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}
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return 0;
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}
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late_initcall_sync(imx_clk_disable_uart);
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