// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/sdram_common.h>
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void sdram_print_dram_type(unsigned char dramtype)
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{
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switch (dramtype) {
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case DDR3:
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printascii("DDR3");
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break;
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case DDR4:
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printascii("DDR4");
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break;
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case LPDDR2:
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printascii("LPDDR2");
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break;
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case LPDDR3:
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printascii("LPDDR3");
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break;
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case LPDDR4:
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printascii("LPDDR4");
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break;
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case LPDDR4X:
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printascii("LPDDR4X");
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break;
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default:
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printascii("Unknown Device");
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break;
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}
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}
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void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base, u32 split)
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{
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u64 cap;
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u32 bg;
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bg = (cap_info->dbw == 0) ? 2 : 1;
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sdram_print_dram_type(base->dramtype);
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printascii(", ");
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printdec(base->ddr_freq);
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printascii("MHz\n");
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printascii("BW=");
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printdec(8 << cap_info->bw);
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printascii(" Col=");
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printdec(cap_info->col);
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printascii(" Bk=");
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printdec(0x1 << cap_info->bk);
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if (base->dramtype == DDR4) {
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printascii(" BG=");
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printdec(1 << bg);
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}
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printascii(" CS0 Row=");
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printdec(cap_info->cs0_row);
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if (cap_info->cs0_high16bit_row !=
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cap_info->cs0_row) {
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printascii("/");
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printdec(cap_info->cs0_high16bit_row);
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}
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if (cap_info->rank > 1) {
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printascii(" CS1 Row=");
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printdec(cap_info->cs1_row);
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if (cap_info->cs1_high16bit_row !=
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cap_info->cs1_row) {
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printascii("/");
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printdec(cap_info->cs1_high16bit_row);
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}
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}
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if (cap_info->rank > 2) {
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printascii(" CS2 Row=");
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printdec(cap_info->cs2_row);
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if (cap_info->cs2_high16bit_row !=
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cap_info->cs2_row) {
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printascii("/");
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printdec(cap_info->cs2_high16bit_row);
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}
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printascii(" CS3 Row=");
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printdec(cap_info->cs3_row);
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if (cap_info->cs3_high16bit_row !=
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cap_info->cs3_row) {
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printascii("/");
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printdec(cap_info->cs3_high16bit_row);
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}
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}
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printascii(" CS=");
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printdec(cap_info->rank);
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printascii(" Die BW=");
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printdec(8 << cap_info->dbw);
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cap = sdram_get_cs_cap(cap_info, 3, base->dramtype);
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if (cap_info->row_3_4)
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cap = cap * 3 / 4;
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else if (split)
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cap = cap / 2 + (split << 24) / 2;
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printascii(" Size=");
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printdec(cap >> 20);
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printascii("MB\n");
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}
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/*
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* cs: 0:cs0
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* 1:cs1
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* else cs0+cs1
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* note: it didn't consider about row_3_4
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*/
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u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type)
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{
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u32 bg;
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u64 cap[4];
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if (dram_type == DDR4)
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/* DDR4 8bit dram BG = 2(4bank groups),
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* 16bit dram BG = 1 (2 bank groups)
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*/
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bg = (cap_info->dbw == 0) ? 2 : 1;
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else
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bg = 0;
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cap[0] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs0_row);
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if (cap_info->rank >= 2)
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cap[1] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs1_row);
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else
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cap[1] = 0;
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if (cap_info->rank == 4) {
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cap[2] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs2_row);
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cap[3] = 1llu << (cap_info->bw + cap_info->col +
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bg + cap_info->bk + cap_info->cs3_row);
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} else {
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cap[2] = 0;
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cap[3] = 0;
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}
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if (cs == 0)
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return cap[0];
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else if (cs == 1)
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return cap[1];
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else
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return (cap[0] + cap[1] + cap[2] + cap[3]);
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}
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/* n: Unit bytes */
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void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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void sdram_org_config(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base,
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u32 *p_os_reg2, u32 *p_os_reg3, u32 channel)
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{
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*p_os_reg2 |= SYS_REG_ENC_DDRTYPE(base->dramtype);
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*p_os_reg2 |= SYS_REG_ENC_NUM_CH(base->num_channels);
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*p_os_reg2 |= SYS_REG_ENC_ROW_3_4(cap_info->row_3_4, channel);
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*p_os_reg2 |= SYS_REG_ENC_CHINFO(channel);
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*p_os_reg2 |= SYS_REG_ENC_RANK(cap_info->rank, channel);
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*p_os_reg2 |= SYS_REG_ENC_COL(cap_info->col, channel);
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*p_os_reg2 |= SYS_REG_ENC_BK(cap_info->bk, channel);
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*p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel);
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*p_os_reg2 |= SYS_REG_ENC_DBW(cap_info->dbw, channel);
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SYS_REG_ENC_CS0_ROW(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel);
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if (cap_info->cs1_row)
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SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, *p_os_reg2,
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*p_os_reg3, channel);
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*p_os_reg3 |= SYS_REG_ENC_CS1_COL(cap_info->col, channel);
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*p_os_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
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}
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void sdram_org_config_v3(struct sdram_cap_info *cap_info,
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struct sdram_base_params *base,
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u32 *p_os_reg2, u32 *p_os_reg3, u32 channel)
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{
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SYS_REG_ENC_DDRTYPE_V3(base->dramtype, *p_os_reg2, *p_os_reg3);
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*p_os_reg2 |= SYS_REG_ENC_NUM_CH_V3((base->num_channels > 2) ?
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2 : base->num_channels);
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*p_os_reg2 |= SYS_REG_ENC_ROW_3_4_V3(cap_info->row_3_4, channel);
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*p_os_reg2 |= SYS_REG_ENC_CHINFO_V3((channel >= 2) ? channel - 2 : channel);
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if (channel == 0 || channel == 2)
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SYS_REG_ENC_CH0_2_RANK_V3(cap_info->rank,
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*p_os_reg2, *p_os_reg3);
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else
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*p_os_reg2 |= SYS_REG_ENC_CH1_3_RANK(cap_info->rank);
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*p_os_reg2 |= SYS_REG_ENC_COL_V3(cap_info->col, channel);
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*p_os_reg2 |= SYS_REG_ENC_BK_V3(cap_info->bk, channel);
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*p_os_reg2 |= SYS_REG_ENC_BW_V3(cap_info->bw, channel);
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*p_os_reg2 |= SYS_REG_ENC_DBW_V3(cap_info->dbw, channel);
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SYS_REG_ENC_CS0_ROW_V3(cap_info->cs0_row, *p_os_reg2, *p_os_reg3, channel);
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if (cap_info->cs1_row)
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SYS_REG_ENC_CS1_ROW_V3(cap_info->cs1_row, *p_os_reg2,
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*p_os_reg3, channel);
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if ((channel == 0 || channel == 2) && cap_info->rank > 2) {
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if (cap_info->cs2_row == cap_info->cs0_row)
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*p_os_reg3 |= SYS_REG_ENC_CS2_DELTA_ROW_V3(0);
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else
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*p_os_reg3 |= SYS_REG_ENC_CS2_DELTA_ROW_V3(1);
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if (cap_info->cs3_row == cap_info->cs0_row)
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*p_os_reg3 |= SYS_REG_ENC_CS3_DELTA_ROW_V3(0);
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else
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*p_os_reg3 |= SYS_REG_ENC_CS3_DELTA_ROW_V3(1);
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}
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*p_os_reg3 |= SYS_REG_ENC_CS1_COL_V3(cap_info->col, channel);
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*p_os_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION_3);
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}
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int sdram_detect_bw(struct sdram_cap_info *cap_info)
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{
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return 0;
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}
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int sdram_detect_cs(struct sdram_cap_info *cap_info)
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{
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return 0;
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}
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int sdram_detect_col(struct sdram_cap_info *cap_info,
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u32 coltmp)
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{
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void __iomem *test_addr;
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u32 col;
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u32 bw = cap_info->bw;
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for (col = coltmp; col >= 9; col -= 1) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (col + bw - 1ul)));
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (col == 8) {
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printascii("col error\n");
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return -1;
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}
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cap_info->col = col;
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return 0;
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}
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int sdram_detect_bank(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp)
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{
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void __iomem *test_addr;
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u32 bk;
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u32 bw = cap_info->bw;
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (coltmp + bktmp + bw - 1ul)));
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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bk = 3;
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else
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bk = 2;
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cap_info->bk = bk;
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return 0;
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}
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/* detect bg for ddr4 */
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int sdram_detect_bg(struct sdram_cap_info *cap_info,
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u32 coltmp)
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{
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void __iomem *test_addr;
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u32 dbw;
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u32 bw = cap_info->bw;
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (coltmp + bw + 1ul)));
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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dbw = 0;
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else
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dbw = 1;
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cap_info->dbw = dbw;
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return 0;
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}
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/* detect dbw for ddr3,lpddr2,lpddr3,lpddr4 */
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int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type)
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{
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u32 row, col, bk, bw, cs_cap, cs;
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u32 die_bw_0 = 0, die_bw_1 = 0;
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if (dram_type == DDR3) {
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if (cap_info->bw == 0)
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cap_info->dbw = 0;
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else
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cap_info->dbw = 1;
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} else if (dram_type == LPDDR4) {
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cap_info->dbw = 1;
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} else if (dram_type == LPDDR3 || dram_type == LPDDR2) {
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row = cap_info->cs0_row;
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col = cap_info->col;
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bk = cap_info->bk;
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cs = cap_info->rank;
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bw = cap_info->bw;
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cs_cap = (1 << (row + col + bk + bw - 20));
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if (bw == 2) {
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if (cs_cap <= 0x20) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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else if (cs_cap <= 0x100) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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else if (cs_cap <= 0x400) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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if (cs > 1) {
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row = cap_info->cs1_row;
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cs_cap = (1 << (row + col + bk + bw - 20));
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if (cs_cap <= 0x20) /* 256Mb */
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die_bw_0 = (col < 9) ? 2 : 1;
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else if (cs_cap <= 0x100) /* 2Gb */
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die_bw_0 = (col < 10) ? 2 : 1;
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else if (cs_cap <= 0x400) /* 8Gb */
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die_bw_0 = (col < 11) ? 2 : 1;
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else
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die_bw_0 = (col < 12) ? 2 : 1;
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}
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} else {
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die_bw_1 = 1;
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die_bw_0 = 1;
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}
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cap_info->dbw = (die_bw_0 > die_bw_1) ? die_bw_0 : die_bw_1;
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}
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return 0;
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}
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int sdram_detect_row(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp, u32 rowtmp)
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{
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u32 row;
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u32 bw = cap_info->bw;
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void __iomem *test_addr;
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for (row = rowtmp; row > 12; row--) {
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writel(0, CONFIG_SYS_SDRAM_BASE);
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test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(1ul << (row + bktmp + coltmp + bw - 1ul)));
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writel(PATTERN, test_addr);
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if ((readl(test_addr) == PATTERN) &&
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(readl(CONFIG_SYS_SDRAM_BASE) == 0))
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break;
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}
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if (row == 12) {
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printascii("row error");
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return -1;
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}
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cap_info->cs0_row = row;
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return 0;
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}
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int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
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u32 coltmp, u32 bktmp)
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{
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u32 row_3_4;
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u32 bw = cap_info->bw;
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u32 row = cap_info->cs0_row;
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void __iomem *test_addr, *test_addr1;
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test_addr = CONFIG_SYS_SDRAM_BASE;
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test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
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(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
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writel(0, test_addr);
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writel(PATTERN, test_addr1);
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if ((readl(test_addr) == 0) && (readl(test_addr1) == PATTERN))
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row_3_4 = 0;
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else
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row_3_4 = 1;
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cap_info->row_3_4 = row_3_4;
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return 0;
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}
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int sdram_detect_high_row(struct sdram_cap_info *cap_info, u32 dramtype)
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{
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unsigned long base_addr;
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u32 cs0_high_row, cs1_high_row, cs;
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u64 cap = 0, cs0_cap = 0;
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u32 i;
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void __iomem *test_addr, *test_addr1;
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#ifdef CONFIG_ROCKCHIP_RK3568
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u32 cs2_high_row, cs3_high_row;
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#endif
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cs = cap_info->rank;
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/* 8bit bandwidth no enable axi split*/
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if (!cap_info->bw) {
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cs0_high_row = cap_info->cs0_row;
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cs1_high_row = cap_info->cs1_row;
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#ifdef CONFIG_ROCKCHIP_RK3568
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if (cs > 2) {
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cs2_high_row = cap_info->cs2_row;
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cs3_high_row = cap_info->cs3_row;
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}
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#endif
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goto out;
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}
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#ifdef CONFIG_ROCKCHIP_RK3568
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if (cs > 2) {
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cs0_high_row = cap_info->cs0_row;
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cs1_high_row = cap_info->cs1_row;
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cs2_high_row = cap_info->cs2_row;
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cs3_high_row = cap_info->cs3_row;
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goto out;
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}
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#endif
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cs0_cap = sdram_get_cs_cap(cap_info, 0, dramtype);
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if (cs == 2) {
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base_addr = CONFIG_SYS_SDRAM_BASE + cs0_cap;
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cap = sdram_get_cs_cap(cap_info, 1, dramtype);
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} else {
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base_addr = CONFIG_SYS_SDRAM_BASE;
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cap = cs0_cap;
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}
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/* detect full bandwidth size */
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for (i = 0; i < 4; i++) {
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test_addr = (void __iomem *)base_addr;
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test_addr1 = (void __iomem *)(base_addr +
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(unsigned long)(cap / (1ul << (i + 1))));
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writel(0x0, test_addr);
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writel(PATTERN, test_addr1);
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if ((readl(test_addr) == 0x0) &&
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(readl(test_addr1) == PATTERN))
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break;
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}
|
if (i == 4 && cs == 1) {
|
printascii("can't support this cap\n");
|
return -1;
|
}
|
|
if (cs == 2) {
|
cs0_high_row = cap_info->cs0_row;
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if (i == 4)
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cs1_high_row = 0;
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else
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cs1_high_row = cap_info->cs1_row - i;
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} else {
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cs0_high_row = cap_info->cs0_row - i;
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cs1_high_row = 0;
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}
|
|
out:
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cap_info->cs0_high16bit_row = cs0_high_row;
|
cap_info->cs1_high16bit_row = cs1_high_row;
|
#ifdef CONFIG_ROCKCHIP_RK3568
|
if (cs > 2) {
|
cap_info->cs2_high16bit_row = cs2_high_row;
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cap_info->cs3_high16bit_row = cs3_high_row;
|
}
|
#endif
|
|
return 0;
|
}
|
|
int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type)
|
{
|
void __iomem *test_addr;
|
u32 row = 0, bktmp, coltmp, bw;
|
ulong cs0_cap;
|
u32 byte_mask;
|
|
if (cap_info->rank == 2) {
|
cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type);
|
|
if (dram_type == DDR4) {
|
if (cap_info->dbw == 0)
|
bktmp = cap_info->bk + 2;
|
else
|
bktmp = cap_info->bk + 1;
|
} else {
|
bktmp = cap_info->bk;
|
}
|
bw = cap_info->bw;
|
coltmp = cap_info->col;
|
|
/*
|
* because px30 support axi split,min bandwidth
|
* is 8bit. if cs0 is 32bit, cs1 may 32bit or 16bit
|
* so we check low 16bit data when detect cs1 row.
|
* if cs0 is 16bit/8bit, we check low 8bit data.
|
*/
|
if (bw == 2)
|
byte_mask = 0xFFFF;
|
else
|
byte_mask = 0xFF;
|
|
/* detect cs1 row */
|
for (row = cap_info->cs0_row; row > 12; row--) {
|
test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE +
|
cs0_cap +
|
(1ul << (row + bktmp + coltmp + bw - 1ul)));
|
writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap);
|
writel(PATTERN, test_addr);
|
|
if (((readl(test_addr) & byte_mask) ==
|
(PATTERN & byte_mask)) &&
|
((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) &
|
byte_mask) == 0)) {
|
break;
|
}
|
}
|
}
|
|
cap_info->cs1_row = row;
|
|
return 0;
|
}
|
