/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3036.h>
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#include <asm/arch/hardware.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3036-cru.h>
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#include <linux/log2.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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VCO_MAX_HZ = 2400U * 1000000,
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VCO_MIN_HZ = 600 * 1000000,
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OUTPUT_MAX_HZ = 2400U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#ifndef CONFIG_SPL_BUILD
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#define RK3036_CLK_DUMP(_id, _name, _iscru) \
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{ \
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.id = _id, \
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.name = _name, \
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.is_cru = _iscru, \
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}
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static const struct rk3036_clk_info clks_dump[] = {
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RK3036_CLK_DUMP(PLL_APLL, "apll", true),
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RK3036_CLK_DUMP(PLL_DPLL, "dpll", true),
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RK3036_CLK_DUMP(PLL_GPLL, "gpll", true),
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};
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#endif
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
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_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
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OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
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#hz "Hz cannot be hit with PLL "\
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"divisors on line " __stringify(__LINE__));
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/* use integer mode*/
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static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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/* All PLLs have same VCO and output frequency range restrictions. */
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uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
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uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
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vco=%u Hz, output=%u Hz\n",
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pll, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_hz, output_hz);
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assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
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output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
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/* use integer mode */
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rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
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/* Power down */
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rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
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rk_clrsetreg(&pll->con0,
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PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
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(div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
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rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT |
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div->refdiv << PLL_REFDIV_SHIFT));
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/* Power Up */
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rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
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/* waiting for pll lock */
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while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
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udelay(1);
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return 0;
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}
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static void rkclk_init(struct rk3036_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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u32 nandc_div;
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/* pll enter slow-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
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APLL_MODE_SLOW << APLL_MODE_SHIFT);
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/* init pll */
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rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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/*
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* select apll as cpu/core clock pll source and
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* set up dependent divisors for PERI and ACLK clocks.
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* core hz : apll = 1:1
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*/
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aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
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assert((aclk_div + 1) * CORE_ACLK_HZ <= APLL_HZ && aclk_div < 0x7);
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pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
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assert((pclk_div + 1) * CORE_PERI_HZ <= APLL_HZ && pclk_div < 0xf);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
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CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
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0 << CORE_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
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aclk_div << CORE_ACLK_DIV_SHIFT |
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pclk_div << CORE_PERI_DIV_SHIFT);
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/*
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* select gpll as pd_bus bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
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assert((aclk_div + 1) * BUS_ACLK_HZ <= GPLL_HZ && aclk_div <= 0x1f);
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pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
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assert((pclk_div + 1) * BUS_PCLK_HZ <= BUS_ACLK_HZ && pclk_div <= 0x7);
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hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
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assert((hclk_div + 1) * BUS_HCLK_HZ <= BUS_ACLK_HZ && hclk_div <= 0x3);
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rk_clrsetreg(&cru->cru_clksel_con[0],
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BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
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BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
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aclk_div << BUS_ACLK_DIV_SHIFT);
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rk_clrsetreg(&cru->cru_clksel_con[1],
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BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
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pclk_div << BUS_PCLK_DIV_SHIFT |
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hclk_div << BUS_HCLK_DIV_SHIFT);
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/*
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* select gpll as pd_peri bus clock source and
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* set up dependent divisors for PCLK/HCLK and ACLK clocks.
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*/
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aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERI_ACLK_HZ <= GPLL_HZ && aclk_div < 0x1f);
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hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
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assert((1 << hclk_div) * PERI_HCLK_HZ <=
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PERI_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
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assert((1 << pclk_div) * PERI_PCLK_HZ <=
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PERI_ACLK_HZ && pclk_div < 0x8);
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rk_clrsetreg(&cru->cru_clksel_con[10],
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PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
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PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
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PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
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pclk_div << PERI_PCLK_DIV_SHIFT |
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hclk_div << PERI_HCLK_DIV_SHIFT |
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aclk_div << PERI_ACLK_DIV_SHIFT);
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nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000);
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rk_clrsetreg(&cru->cru_clksel_con[16],
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NANDC_PLL_MASK | NANDC_DIV_MASK,
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NANDC_SEL_GPLL << NANDC_PLL_SHIFT |
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nandc_div << NANDC_DIV_SHIFT);
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/* PLL enter normal-mode */
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rk_clrsetreg(&cru->cru_mode_con,
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GPLL_MODE_MASK | APLL_MODE_MASK,
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GPLL_MODE_NORM << GPLL_MODE_SHIFT |
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APLL_MODE_NORM << APLL_MODE_SHIFT);
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}
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/* Get pll rate by id */
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static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
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enum rk_clk_id clk_id)
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{
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uint32_t refdiv, fbdiv, postdiv1, postdiv2;
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uint32_t con;
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int pll_id = rk_pll_id(clk_id);
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struct rk3036_pll *pll = &cru->pll[pll_id];
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static u8 clk_shift[CLK_COUNT] = {
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0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
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GPLL_MODE_SHIFT, 0xff
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};
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static u32 clk_mask[CLK_COUNT] = {
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0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
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GPLL_MODE_MASK, 0xffffffff
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};
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uint shift;
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uint mask;
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con = readl(&cru->cru_mode_con);
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shift = clk_shift[clk_id];
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mask = clk_mask[clk_id];
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switch ((con & mask) >> shift) {
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case GPLL_MODE_SLOW:
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return OSC_HZ;
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case GPLL_MODE_NORM:
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/* normal mode */
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con = readl(&pll->con0);
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postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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con = readl(&pll->con1);
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postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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case GPLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
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int periph)
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{
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uint src_rate;
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uint div, mux;
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u32 con;
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
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div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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con = readl(&cru->cru_clksel_con[12]);
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mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
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div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
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return DIV_TO_RATE(src_rate, div) / 2;
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}
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static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
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int periph, uint freq)
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{
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int src_clk_div;
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int mux;
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debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
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/* mmc clock auto divide 2 in internal */
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src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
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if (src_clk_div > 128) {
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src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
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assert(src_clk_div - 1 < 128);
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mux = EMMC_SEL_24M;
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} else {
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mux = EMMC_SEL_GPLL;
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}
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switch (periph) {
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case HCLK_EMMC:
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case SCLK_EMMC:
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rk_clrsetreg(&cru->cru_clksel_con[12],
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EMMC_PLL_MASK | EMMC_DIV_MASK,
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mux << EMMC_PLL_SHIFT |
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(src_clk_div - 1) << EMMC_DIV_SHIFT);
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break;
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case HCLK_SDIO:
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case SCLK_SDIO:
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rk_clrsetreg(&cru->cru_clksel_con[11],
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MMC0_PLL_MASK | MMC0_DIV_MASK,
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mux << MMC0_PLL_SHIFT |
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(src_clk_div - 1) << MMC0_DIV_SHIFT);
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break;
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default:
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return -EINVAL;
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}
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return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
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}
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static ulong rk3036_spi_get_clk(struct rk3036_cru *cru, uint clk_general_rate)
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{
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u32 div, con;
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con = readl(&cru->cru_clksel_con[25]);
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div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT;
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return DIV_TO_RATE(clk_general_rate, div);
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}
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static ulong rk3036_spi_set_clk(struct rk3036_cru *cru,
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uint clk_general_rate,
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ulong hz)
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{
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int div;
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div = DIV_ROUND_UP(clk_general_rate, hz);
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assert(div - 1 < 128);
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rk_clrsetreg(&cru->cru_clksel_con[25],
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SPI_PLL_SEL_MASK | SPI_DIV_MASK,
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SPI_PLL_SEL_GPLL << SPI_PLL_SEL_SHIFT |
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(div - 1) << SPI_DIV_SHIFT);
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return rk3036_spi_get_clk(cru, clk_general_rate);
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}
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static ulong rockchip_dclk_lcdc_get_clk(struct rk3036_cru *cru,
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uint clk_general_rate)
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{
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u32 con, div, sel, parent;
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con = readl(&cru->cru_clksel_con[28]);
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div = (con & LCDC_DCLK_DIV_MASK) >> LCDC_DCLK_DIV_SHIFT;
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sel = (con & LCDC_DCLK_SEL_MASK) >> LCDC_DCLK_SEL_SHIFT;
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if (sel == LCDC_DCLK_SEL_GPLL)
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parent = clk_general_rate;
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else
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return -ENOENT;
|
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return DIV_TO_RATE(parent, div);
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}
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static ulong rockchip_dclk_lcdc_set_clk(struct rk3036_cru *cru,
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uint clk_general_rate, uint freq)
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{
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int src_clk_div;
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src_clk_div = DIV_ROUND_UP(clk_general_rate, freq);
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assert(src_clk_div - 1 <= 255);
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rk_clrsetreg(&cru->cru_clksel_con[28],
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LCDC_DCLK_SEL_MASK | LCDC_DCLK_DIV_MASK,
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LCDC_DCLK_SEL_GPLL << LCDC_DCLK_SEL_SHIFT |
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(src_clk_div - 1) << LCDC_DCLK_DIV_SHIFT);
|
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return rockchip_dclk_lcdc_get_clk(cru, clk_general_rate);
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}
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static ulong rockchip_aclk_lcdc_get_clk(struct rk3036_cru *cru,
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uint clk_general_rate)
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{
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u32 con, div, sel, parent;
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con = readl(&cru->cru_clksel_con[31]);
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div = (con & LCDC_ACLK_DIV_MASK) >> LCDC_ACLK_DIV_SHIFT;
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sel = (con & LCDC_ACLK_SEL_MASK) >> LCDC_ACLK_SEL_SHIFT;
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if (sel == LCDC_ACLK_SEL_GPLL)
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parent = clk_general_rate;
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else
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return -ENOENT;
|
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return DIV_TO_RATE(parent, div);
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}
|
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static ulong rockchip_aclk_lcdc_set_clk(struct rk3036_cru *cru,
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uint clk_general_rate, uint freq)
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{
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int src_clk_div;
|
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src_clk_div = DIV_ROUND_UP(clk_general_rate, freq);
|
assert(src_clk_div - 1 <= 31);
|
|
rk_clrsetreg(&cru->cru_clksel_con[31],
|
LCDC_ACLK_SEL_MASK | LCDC_ACLK_DIV_MASK,
|
LCDC_ACLK_SEL_GPLL << LCDC_ACLK_SEL_SHIFT |
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(src_clk_div - 1) << LCDC_ACLK_DIV_SHIFT);
|
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return rockchip_aclk_lcdc_get_clk(cru, clk_general_rate);
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}
|
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static ulong rk3036_peri_get_clk(struct rk3036_clk_priv *priv, ulong clk_id,
|
uint clk_general_rate)
|
{
|
struct rk3036_cru *cru = priv->cru;
|
u32 div, con, parent;
|
|
switch (clk_id) {
|
case ACLK_PERI:
|
con = readl(&cru->cru_clksel_con[10]);
|
div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;
|
parent = clk_general_rate;
|
break;
|
case PCLK_PWM:
|
con = readl(&cru->cru_clksel_con[10]);
|
div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;
|
parent = rk3036_peri_get_clk(priv, ACLK_PERI, clk_general_rate);
|
break;
|
default:
|
printf("do not support this peripheral bus\n");
|
return -EINVAL;
|
}
|
|
return DIV_TO_RATE(parent, div);
|
}
|
|
static ulong rk3036_peri_set_clk(struct rk3036_clk_priv *priv,
|
ulong clk_id, uint clk_general_rate,
|
uint hz)
|
{
|
struct rk3036_cru *cru = priv->cru;
|
int src_clk_div;
|
|
switch (clk_id) {
|
case ACLK_PERI:
|
src_clk_div = DIV_ROUND_UP(clk_general_rate, hz);
|
assert(src_clk_div - 1 < 32);
|
rk_clrsetreg(&cru->cru_clksel_con[10],
|
PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK,
|
PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
|
(src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);
|
break;
|
case PCLK_PWM:
|
src_clk_div = DIV_ROUND_UP(rk3036_peri_get_clk(priv,
|
ACLK_PERI,
|
clk_general_rate),
|
hz);
|
assert(src_clk_div - 1 < 8);
|
rk_clrsetreg(&cru->cru_clksel_con[10],
|
PERI_PCLK_DIV_MASK,
|
(src_clk_div - 1) << PERI_PCLK_DIV_SHIFT);
|
break;
|
default:
|
printf("do not support this peripheral bus\n");
|
return -EINVAL;
|
}
|
|
return rk3036_peri_get_clk(priv, clk_id, clk_general_rate);
|
}
|
|
static ulong rk3036_clk_get_rate(struct clk *clk)
|
{
|
struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
|
ulong gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
|
switch (clk->id) {
|
case 0 ... 63:
|
return rkclk_pll_get_rate(priv->cru, clk->id);
|
case SCLK_LCDC:
|
return rockchip_dclk_lcdc_get_clk(priv->cru, gclk_rate);
|
case ACLK_LCDC:
|
return rockchip_aclk_lcdc_get_clk(priv->cru, gclk_rate);
|
case SCLK_SPI:
|
return rk3036_spi_get_clk(priv->cru, gclk_rate);
|
case PCLK_PWM:
|
return rk3036_peri_get_clk(priv, clk->id, gclk_rate);
|
default:
|
return -ENOENT;
|
}
|
}
|
|
static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
|
{
|
struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
|
ulong new_rate, gclk_rate;
|
|
gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
|
switch (clk->id) {
|
case 0 ... 63:
|
return 0;
|
case HCLK_EMMC:
|
case SCLK_EMMC:
|
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
|
clk->id, rate);
|
break;
|
case SCLK_LCDC:
|
new_rate = rockchip_dclk_lcdc_set_clk(priv->cru, gclk_rate,
|
rate);
|
break;
|
case ACLK_LCDC:
|
new_rate = rockchip_aclk_lcdc_set_clk(priv->cru, gclk_rate,
|
rate);
|
break;
|
case SCLK_SPI:
|
new_rate = rk3036_spi_set_clk(priv->cru, gclk_rate,
|
rate);
|
break;
|
case PCLK_PWM:
|
new_rate = rk3036_peri_set_clk(priv, clk->id, gclk_rate,
|
rate);
|
break;
|
default:
|
return -ENOENT;
|
}
|
|
return new_rate;
|
}
|
|
static struct clk_ops rk3036_clk_ops = {
|
.get_rate = rk3036_clk_get_rate,
|
.set_rate = rk3036_clk_set_rate,
|
};
|
|
static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
|
{
|
struct rk3036_clk_priv *priv = dev_get_priv(dev);
|
|
priv->cru = dev_read_addr_ptr(dev);
|
|
return 0;
|
}
|
|
static int rk3036_clk_probe(struct udevice *dev)
|
{
|
struct rk3036_clk_priv *priv = dev_get_priv(dev);
|
|
priv->sync_kernel = false;
|
if (!priv->armclk_enter_hz)
|
priv->armclk_enter_hz = rkclk_pll_get_rate(priv->cru,
|
CLK_ARM);
|
rkclk_init(priv->cru);
|
if (!priv->armclk_init_hz)
|
priv->armclk_init_hz = rkclk_pll_get_rate(priv->cru,
|
CLK_ARM);
|
|
return 0;
|
}
|
|
static int rk3036_clk_bind(struct udevice *dev)
|
{
|
int ret;
|
struct udevice *sys_child, *sf_child;
|
struct sysreset_reg *priv;
|
struct softreset_reg *sf_priv;
|
|
/* The reset driver does not have a device node, so bind it here */
|
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
|
&sys_child);
|
if (ret) {
|
debug("Warning: No sysreset driver: ret=%d\n", ret);
|
} else {
|
priv = malloc(sizeof(struct sysreset_reg));
|
priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
|
cru_glb_srst_fst_value);
|
priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
|
cru_glb_srst_snd_value);
|
sys_child->priv = priv;
|
}
|
|
ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
|
dev_ofnode(dev), &sf_child);
|
if (ret) {
|
debug("Warning: No rockchip reset driver: ret=%d\n", ret);
|
} else {
|
sf_priv = malloc(sizeof(struct softreset_reg));
|
sf_priv->sf_reset_offset = offsetof(struct rk3036_cru,
|
cru_softrst_con[0]);
|
sf_priv->sf_reset_num = 9;
|
sf_child->priv = sf_priv;
|
}
|
|
return 0;
|
}
|
|
static const struct udevice_id rk3036_clk_ids[] = {
|
{ .compatible = "rockchip,rk3036-cru" },
|
{ }
|
};
|
|
U_BOOT_DRIVER(rockchip_rk3036_cru) = {
|
.name = "clk_rk3036",
|
.id = UCLASS_CLK,
|
.of_match = rk3036_clk_ids,
|
.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
|
.ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
|
.ops = &rk3036_clk_ops,
|
.bind = rk3036_clk_bind,
|
.probe = rk3036_clk_probe,
|
};
|
|
#ifndef CONFIG_SPL_BUILD
|
/**
|
* soc_clk_dump() - Print clock frequencies
|
* Returns zero on success
|
*
|
* Implementation for the clk dump command.
|
*/
|
int soc_clk_dump(void)
|
{
|
struct udevice *cru_dev;
|
struct rk3036_clk_priv *priv;
|
const struct rk3036_clk_info *clk_dump;
|
struct clk clk;
|
unsigned long clk_count = ARRAY_SIZE(clks_dump);
|
unsigned long rate;
|
int i, ret;
|
|
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
DM_GET_DRIVER(rockchip_rk3036_cru),
|
&cru_dev);
|
if (ret) {
|
printf("%s failed to get cru device\n", __func__);
|
return ret;
|
}
|
|
priv = dev_get_priv(cru_dev);
|
printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
|
priv->sync_kernel ? "sync kernel" : "uboot",
|
priv->armclk_enter_hz / 1000,
|
priv->armclk_init_hz / 1000,
|
priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
|
priv->set_armclk_rate ? " KHz" : "N/A");
|
for (i = 0; i < clk_count; i++) {
|
clk_dump = &clks_dump[i];
|
if (clk_dump->name) {
|
clk.id = clk_dump->id;
|
if (clk_dump->is_cru)
|
ret = clk_request(cru_dev, &clk);
|
if (ret < 0)
|
return ret;
|
|
rate = clk_get_rate(&clk);
|
clk_free(&clk);
|
if (i == 0) {
|
if (rate < 0)
|
printf(" %s %s\n", clk_dump->name,
|
"unknown");
|
else
|
printf(" %s %lu KHz\n", clk_dump->name,
|
rate / 1000);
|
} else {
|
if (rate < 0)
|
printf(" %s %s\n", clk_dump->name,
|
"unknown");
|
else
|
printf(" %s %lu KHz\n", clk_dump->name,
|
rate / 1000);
|
}
|
}
|
}
|
|
return 0;
|
}
|
#endif
|
