/*
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* (C) Copyright 2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra124 high-level function multiplexing */
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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int funcmux_select(enum periph_id id, int config)
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{
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int bad_config = config != FUNCMUX_DEFAULT;
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switch (id) {
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case PERIPH_ID_UART4:
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switch (config) {
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case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
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pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
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pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
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pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
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pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
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pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
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pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
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pinmux_tristate_disable(PMUX_PINGRP_PJ7);
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pinmux_tristate_disable(PMUX_PINGRP_PB0);
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pinmux_tristate_disable(PMUX_PINGRP_PB1);
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pinmux_tristate_disable(PMUX_PINGRP_PK7);
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break;
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}
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break;
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case PERIPH_ID_UART1:
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switch (config) {
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case FUNCMUX_UART1_KBC:
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pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
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PMUX_FUNC_UARTA);
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pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
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PMUX_FUNC_UARTA);
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pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
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pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
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pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
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pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
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break;
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}
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break;
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/* Add other periph IDs here as needed */
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default:
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debug("%s: invalid periph_id %d", __func__, id);
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return -1;
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}
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if (bad_config) {
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debug("%s: invalid config %d for periph_id %d", __func__,
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config, id);
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return -1;
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}
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return 0;
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}
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