/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <boot_rkimg.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <key.h>
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#include <led.h>
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#include <misc.h>
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#include <ram.h>
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#include <spl.h>
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#include <optee_include/OpteeClientInterface.h>
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#include <power/fuel_gauge.h>
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#include <asm/arch/bootrom.h>
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#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
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#include <asm/arch/rk_atags.h>
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#endif
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#include <asm/arch/sdram.h>
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#include <asm/arch/boot_mode.h>
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#include <asm/arch-rockchip/sys_proto.h>
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#include <asm/io.h>
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#include <asm/arch/param.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_return_to_bootrom(void)
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{
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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__weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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};
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const char *board_spl_was_booted_from(void)
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{
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u32 bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
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const char *bootdevice_ofpath = NULL;
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if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
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bootdevice_ofpath = boot_devices[bootdevice_brom_id];
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if (bootdevice_ofpath)
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debug("%s: brom_bootdevice_id %x maps to '%s'\n",
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__func__, bootdevice_brom_id, bootdevice_ofpath);
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else
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debug("%s: failed to resolve brom_bootdevice_id %x\n",
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__func__, bootdevice_brom_id);
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return bootdevice_ofpath;
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}
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u32 spl_boot_device(void)
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{
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u32 boot_device = BOOT_DEVICE_MMC1;
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#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
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defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
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defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
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return BOOT_DEVICE_SPI;
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#endif
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if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM))
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return BOOT_DEVICE_BOOTROM;
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return boot_device;
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}
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u32 spl_boot_mode(const u32 boot_device)
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{
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return MMCSD_MODE_RAW;
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}
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__weak void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
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if ( reg & 0x1 )
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return;
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#ifndef CONFIG_ARM64
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(COUNTER_FREQUENCY));
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#endif
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writel(0, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4);
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writel(1, CONFIG_ROCKCHIP_STIMER_BASE + 0x10);
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}
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__weak int arch_cpu_init(void)
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{
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return 0;
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}
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__weak int rk_board_init_f(void)
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{
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return 0;
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}
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#ifndef CONFIG_SPL_LIBGENERIC_SUPPORT
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void udelay(unsigned long usec)
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{
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__udelay(usec);
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}
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void hang(void)
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{
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bootstage_error(BOOTSTAGE_ID_NEED_RESET);
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for (;;)
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;
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}
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/**
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* memset - Fill a region of memory with the given value
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* @s: Pointer to the start of the area.
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* @c: The byte to fill the area with
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* @count: The size of the area.
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*
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* Do not use memset() to access IO space, use memset_io() instead.
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*/
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void *memset(void *s, int c, size_t count)
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{
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unsigned long *sl = (unsigned long *)s;
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char *s8;
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#if !CONFIG_IS_ENABLED(TINY_MEMSET)
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unsigned long cl = 0;
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int i;
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/* do it one word at a time (32 bits or 64 bits) while possible */
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if (((ulong)s & (sizeof(*sl) - 1)) == 0) {
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for (i = 0; i < sizeof(*sl); i++) {
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cl <<= 8;
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cl |= c & 0xff;
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}
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while (count >= sizeof(*sl)) {
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*sl++ = cl;
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count -= sizeof(*sl);
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}
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}
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#endif /* fill 8 bits at a time */
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s8 = (char *)sl;
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while (count--)
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*s8++ = c;
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return s;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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#ifdef CONFIG_SPL_FRAMEWORK
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int ret;
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#if !defined(CONFIG_SUPPORT_TPL)
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struct udevice *dev;
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#endif
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#endif
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gd->flags = dummy;
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rockchip_stimer_init();
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#define EARLY_UART
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#if defined(EARLY_UART) && defined(CONFIG_DEBUG_UART)
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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if (!gd->serial.using_pre_serial &&
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!(gd->flags & GD_FLG_DISABLE_CONSOLE))
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debug_uart_init();
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printascii("U-Boot SPL board init");
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#endif
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gd->sys_start_tick = get_ticks();
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#ifdef CONFIG_SPL_FRAMEWORK
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ret = spl_early_init();
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if (ret) {
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printf("spl_early_init() failed: %d\n", ret);
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hang();
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}
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#if !defined(CONFIG_SUPPORT_TPL)
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debug("\nspl:init dram\n");
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return;
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}
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#endif
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preloader_console_init();
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#else
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/* Some SoCs like rk3036 does not use any frame work */
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sdram_init();
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#endif
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arch_cpu_init();
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rk_board_init_f();
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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int board_init_f_boot_flags(void)
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{
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int boot_flags = 0;
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#ifdef CONFIG_FPGA_ROCKCHIP
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arch_fpga_init();
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#endif
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#ifdef CONFIG_PSTORE
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param_parse_pstore();
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#endif
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/* pre-loader serial */
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#if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \
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defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS)
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struct tag *t;
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t = atags_get_tag(ATAG_SERIAL);
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if (t) {
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gd->serial.using_pre_serial = 1;
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gd->serial.enable = t->u.serial.enable;
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gd->serial.baudrate = t->u.serial.baudrate;
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gd->serial.addr = t->u.serial.addr;
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gd->serial.id = t->u.serial.id;
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gd->baudrate = t->u.serial.baudrate;
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if (!t->u.serial.enable)
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boot_flags |= GD_FLG_DISABLE_CONSOLE;
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debug("preloader: enable=%d, addr=0x%x, baudrate=%d, id=%d\n",
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t->u.serial.enable, (u32)t->u.serial.addr,
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t->u.serial.baudrate, t->u.serial.id);
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} else
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#endif
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{
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gd->baudrate = CONFIG_BAUDRATE;
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gd->serial.baudrate = CONFIG_BAUDRATE;
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gd->serial.addr = CONFIG_DEBUG_UART_BASE;
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}
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/* The highest priority to turn off (override) console */
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#if defined(CONFIG_DISABLE_CONSOLE)
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boot_flags |= GD_FLG_DISABLE_CONSOLE;
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#endif
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return boot_flags;
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}
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#ifdef CONFIG_SPL_BOARD_INIT
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__weak int rk_spl_board_init(void)
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{
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return 0;
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}
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static int setup_led(void)
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{
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#ifdef CONFIG_SPL_LED
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struct udevice *dev;
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
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if (!led_name)
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return 0;
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ret = led_get_by_label(led_name, &dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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ret = led_set_state(dev, LEDST_ON);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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void spl_board_init(void)
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{
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int ret;
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ret = setup_led();
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if (ret) {
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debug("LED ret=%d\n", ret);
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hang();
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}
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rk_spl_board_init();
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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return;
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}
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#endif
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
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atags_set_bootdev_by_spl_bootdevice(spl_image->boot_device);
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#endif
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return;
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}
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#ifdef CONFIG_SPL_KERNEL_BOOT
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static int spl_rockchip_dnl_key_pressed(void)
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{
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#if defined(CONFIG_SPL_INPUT)
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return key_read(KEY_VOLUMEUP);
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#else
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return 0;
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#endif
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}
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#ifdef CONFIG_SPL_DM_FUEL_GAUGE
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bool spl_is_low_power(void)
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{
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struct udevice *dev;
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int ret, voltage;
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ret = uclass_get_device(UCLASS_FG, 0, &dev);
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if (ret) {
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debug("Get charge display failed, ret=%d\n", ret);
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return false;
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}
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voltage = fuel_gauge_get_voltage(dev);
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if (voltage >= CONFIG_SPL_POWER_LOW_VOLTAGE_THRESHOLD)
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return false;
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return true;
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}
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#endif
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void spl_next_stage(struct spl_image_info *spl)
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{
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uint32_t reg_boot_mode;
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if (spl_rockchip_dnl_key_pressed()) {
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spl->next_stage = SPL_NEXT_STAGE_UBOOT;
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return;
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}
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#ifdef CONFIG_SPL_DM_FUEL_GAUGE
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if (spl_is_low_power()) {
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spl->next_stage = SPL_NEXT_STAGE_UBOOT;
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return;
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}
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#endif
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reg_boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
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switch (reg_boot_mode) {
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case BOOT_COLD:
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case BOOT_PANIC:
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case BOOT_WATCHDOG:
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case BOOT_NORMAL:
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case BOOT_RECOVERY:
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spl->next_stage = SPL_NEXT_STAGE_KERNEL;
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break;
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default:
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spl->next_stage = SPL_NEXT_STAGE_UBOOT;
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}
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}
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#endif
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#ifdef CONFIG_SPL_KERNEL_BOOT
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const char *spl_kernel_partition(struct spl_image_info *spl,
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struct spl_load_info *info)
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{
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struct bootloader_message *bmsg = NULL;
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u32 boot_mode;
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int ret, cnt;
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u32 sector = 0;
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#ifdef CONFIG_SPL_LIBDISK_SUPPORT
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disk_partition_t part_info;
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ret = part_get_info_by_name(info->dev, PART_MISC, &part_info);
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if (ret >= 0)
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sector = part_info.start;
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#else
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sector = CONFIG_SPL_MISC_SECTOR;
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#endif
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if (sector) {
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cnt = DIV_ROUND_UP(sizeof(*bmsg), info->bl_len);
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bmsg = memalign(ARCH_DMA_MINALIGN, cnt * info->bl_len);
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ret = info->read(info, sector + BCB_MESSAGE_BLK_OFFSET,
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cnt, bmsg);
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if (ret == cnt && !strcmp(bmsg->command, "boot-recovery")) {
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free(bmsg);
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return PART_RECOVERY;
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} else {
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free(bmsg);
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}
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}
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boot_mode = readl((void *)CONFIG_ROCKCHIP_BOOT_MODE_REG);
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return (boot_mode == BOOT_RECOVERY) ? PART_RECOVERY : PART_BOOT;
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}
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#endif
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void spl_hang_reset(void)
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{
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printf("# Reset the board to bootrom #\n");
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#if defined(CONFIG_SPL_SYSRESET) && defined(CONFIG_SPL_DRIVERS_MISC_SUPPORT)
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/* reset is available after dm setup */
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if (gd->flags & GD_FLG_SPL_EARLY_INIT) {
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writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG);
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do_reset(NULL, 0, 0, NULL);
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}
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#endif
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}
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#ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
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int fit_read_otp_rollback_index(uint32_t fit_index, uint32_t *otp_index)
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{
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int ret = 0;
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*otp_index = 0;
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#if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
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struct udevice *dev;
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u32 index, i, otp_version;
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u32 bit_count;
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dev = misc_otp_get_device(OTP_S);
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if (!dev)
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return -ENODEV;
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otp_version = 0;
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for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
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if (misc_otp_read(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
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&index,
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4)) {
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printf("Can't read rollback index\n");
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return -EIO;
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}
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bit_count = fls(index);
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otp_version += bit_count;
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}
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*otp_index = otp_version;
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#endif
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return ret;
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}
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static int fit_write_otp_rollback_index(u32 fit_index)
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{
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#if defined(CONFIG_SPL_ROCKCHIP_SECURE_OTP)
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struct udevice *dev;
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u32 index, i, otp_index;
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if (!fit_index)
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return 0;
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if (fit_index > OTP_UBOOT_ROLLBACK_WORDS * 32)
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return -EINVAL;
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dev = misc_otp_get_device(OTP_S);
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if (!dev)
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return -ENODEV;
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if (fit_read_otp_rollback_index(fit_index, &otp_index))
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return -EIO;
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if (otp_index < fit_index) {
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/* Write new SW version to otp */
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for (i = 0; i < OTP_UBOOT_ROLLBACK_WORDS; i++) {
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/*
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* If fit_index is equal to 0, then execute 0xffffffff >> 32.
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* But the operand can only be 0 - 31. The "0xffffffff >> 32" is
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* actually be "0xffffffff >> 0".
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*/
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if (!fit_index)
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break;
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/* convert to base-1 representation */
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index = 0xffffffff >> (OTP_ALL_ONES_NUM_BITS -
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min(fit_index, (u32)OTP_ALL_ONES_NUM_BITS));
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fit_index -= min(fit_index,
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(u32)OTP_ALL_ONES_NUM_BITS);
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if (index) {
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if (misc_otp_write(dev, OTP_UBOOT_ROLLBACK_OFFSET + i * 4,
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&index,
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4)) {
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printf("Can't write rollback index\n");
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return -EIO;
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}
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}
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}
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}
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#endif
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return 0;
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}
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#endif
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int spl_board_prepare_for_jump(struct spl_image_info *spl_image)
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{
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#ifdef CONFIG_SPL_FIT_ROLLBACK_PROTECT
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int ret;
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ret = fit_write_otp_rollback_index(gd->rollback_index);
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if (ret) {
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panic("Failed to write fit rollback index %d, ret=%d",
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gd->rollback_index, ret);
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}
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#endif
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#ifdef CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS
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misc_decompress_cleanup();
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#endif
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return 0;
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}
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