/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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* Copyright (c) 2016 Andreas Färber
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/arch/bootrom.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3368.h>
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#include <asm/arch/grf_rk3368.h>
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#include <syscon.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMEM_BASE 0xFF8C0000
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/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 8K) */
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#define MCU_SRAM_BASE (IMEM_BASE + 1024 * 8)
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#define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
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/* exsram may using by mcu to accessing dram(0x0-0x20000000) */
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#define MCU_EXSRAM_BASE (0)
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#define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
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/* experi no used, reserved value = 0 */
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#define MCU_EXPERI_BASE (0)
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#define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
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#define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
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#define DDR_LATENCY_BASE (0xffac0000 + 0x14)
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#define DDR_READ_LATENCY_VALUE 0x34
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#define CPU_AXI_QOS_PRIORITY_BASE 0xffad0300
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#define CPU_AXI_QOS_PRIORITY 0x08
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#define QOS_PRIORITY_LEVEL_H 2
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#define QOS_PRIORITY_LEVEL_L 2
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#define ISP_R0_QOS_BASE 0xffad0080
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#define QOS_ISP_R0_PRIORITY_LEVEL_H 1
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#define QOS_ISP_R0_PRIORITY_LEVEL_L 1
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#define ISP_R1_QOS_BASE 0xffad0100
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#define QOS_ISP_R1_PRIORITY_LEVEL_H 1
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#define QOS_ISP_R1_PRIORITY_LEVEL_L 1
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#define ISP_W0_QOS_BASE 0xffad0180
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#define QOS_ISP_W0_PRIORITY_LEVEL_H 3
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#define QOS_ISP_W0_PRIORITY_LEVEL_L 3
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#define ISP_W1_QOS_BASE 0xffad0200
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#define QOS_ISP_W1_PRIORITY_LEVEL_H 3
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#define QOS_ISP_W1_PRIORITY_LEVEL_L 3
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/* cpu axi qos priority */
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#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
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((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
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#define GRF_SOC_CON15 0xff77043c
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#define PMU_GRF_SOC_CON0 0xff738100
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static struct mm_region rk3368_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xfe000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xfe000000UL,
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.phys = 0xfe000000UL,
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.size = 0x02000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3368_mem_map;
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
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};
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#ifdef CONFIG_ARCH_EARLY_INIT_R
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static int mcu_init(void)
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{
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struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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struct rk3368_cru *cru = rockchip_get_cru();
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rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
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MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
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MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
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MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
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MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
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MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
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rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
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MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
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rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
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(MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
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(5 << MCU_CLK_DIV_SHIFT));
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/* mcu dereset, for start running */
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rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
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return 0;
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}
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int arch_early_init_r(void)
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{
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return mcu_init();
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}
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#endif
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void board_debug_uart_init(void)
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{
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/*
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* N.B.: This is called before the device-model has been
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* initialised. For this reason, we can not access
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* the GRF address range using the syscon API.
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*/
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struct rk3368_grf * const grf __maybe_unused =
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(struct rk3368_grf * const)0xff770000;
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enum {
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/* UART0 */
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GPIO2D1_MASK = GENMASK(3, 2),
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART0_SOUT = (1 << 2),
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GPIO2D0_MASK = GENMASK(1, 0),
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GPIO2D0_GPIO = 0,
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GPIO2D0_UART0_SIN = (1 << 0),
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/* UART2 */
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GPIO2A6_MASK = GENMASK(13, 12),
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GPIO2A6_GPIO = 0,
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GPIO2A6_UART0_SIN = (1 << 13),
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GPIO2A6_UART2_SIN = (2 << 12),
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GPIO2A5_MASK = GENMASK(11, 10),
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GPIO2A5_GPIO = 0,
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GPIO2A5_UART0_SOUT = (1 << 11),
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GPIO2A5_UART2_SOUT = (2 << 10),
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};
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3368 */
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D0_MASK, GPIO2D0_UART0_SIN);
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
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struct rk3368_pmu_grf * const pmugrf __maybe_unused =
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(struct rk3368_pmu_grf * const)0xff738000;
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enum {
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/* UART4 */
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GPIO0D2_MASK = GENMASK(5, 4),
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GPIO0D2_GPIO = 0,
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GPIO0D2_UART4_SOUT = (3 << 4),
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GPIO0D3_MASK = GENMASK(7, 6),
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GPIO0D3_GPIO = 0,
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GPIO0D3_UART4_SIN = (3 << 6),
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};
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/* Enable early UART4 on the PX5 */
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rk_clrsetreg(&pmugrf->gpio0d_iomux,
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GPIO0D2_MASK | GPIO0D3_MASK,
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GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
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#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
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/* Enable early UART2 on the RK3368 */
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A6_MASK, GPIO2A6_UART2_SIN);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
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#endif
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}
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#ifndef CONFIG_TPL_BUILD
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static void cpu_axi_qos_prority_level_config(void)
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{
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u32 level;
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/* Set lcdc cpu axi qos priority level */
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level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_PRIORITY_LEVEL_H,
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QOS_PRIORITY_LEVEL_L);
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writel(level, CPU_AXI_QOS_PRIORITY_BASE + CPU_AXI_QOS_PRIORITY);
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/* Set cpu isp r0 qos priority level */
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level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_R0_PRIORITY_LEVEL_H,
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QOS_ISP_R0_PRIORITY_LEVEL_L);
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writel(level, ISP_R0_QOS_BASE + CPU_AXI_QOS_PRIORITY);
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/* Set cpu isp r1 qos priority level */
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level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_R1_PRIORITY_LEVEL_H,
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QOS_ISP_R1_PRIORITY_LEVEL_L);
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writel(level, ISP_R1_QOS_BASE + CPU_AXI_QOS_PRIORITY);
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/* Set cpu isp w0 qos priority level */
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level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_W0_PRIORITY_LEVEL_H,
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QOS_ISP_W0_PRIORITY_LEVEL_L);
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writel(level, ISP_W0_QOS_BASE + CPU_AXI_QOS_PRIORITY);
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/* Set cpu isp w1 qos priority level */
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level = CPU_AXI_QOS_PRIORITY_LEVEL(QOS_ISP_W1_PRIORITY_LEVEL_H,
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QOS_ISP_W1_PRIORITY_LEVEL_L);
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writel(level, ISP_W1_QOS_BASE + CPU_AXI_QOS_PRIORITY);
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* The SPL (and also the full U-Boot stage on the RK3368) will run in
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* secure mode (i.e. EL3) and an ATF will eventually be booted before
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* starting up the operating system... so we can initialize the SGRF
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* here and rely on the ATF installing the final (secure) policy
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* later.
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*/
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static inline uintptr_t sgrf_soc_con_addr(unsigned no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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return SGRF_BASE + sizeof(u32) * no;
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}
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static inline uintptr_t sgrf_busdmac_addr(unsigned no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
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const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
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return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
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}
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static void sgrf_init(void)
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{
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struct rk3368_cru * const cru =
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(struct rk3368_cru * const)rockchip_get_cru();
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const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
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const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
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const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
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/* Set all configurable IP to 'non secure'-mode */
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rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
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/*
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* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
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* Original comment: "ddr space set no secure mode"
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*/
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rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
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/* Set 'secure dma' to 'non secure'-mode */
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rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
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rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
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dsb(); /* barrier */
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rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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dsb(); /* barrier */
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udelay(10);
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rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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}
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#endif
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int arch_cpu_init(void)
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{
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/* DDR read latency config */
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writel(DDR_READ_LATENCY_VALUE, DDR_LATENCY_BASE);
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/* PWMs select rkpwm clock source */
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rk_setreg(GRF_SOC_CON15, 1 << 12);
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/* PWM2 select 32KHz clock source */
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rk_clrreg(PMU_GRF_SOC_CON0, 1 << 7);
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/* Enable force jtag */
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rk_setreg(GRF_SOC_CON15, 1 << 13);
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/* Cpu axi qos config */
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cpu_axi_qos_prority_level_config();
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#ifdef CONFIG_SPL_BUILD
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/* Reset security, so we can use DMA in the MMC drivers */
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sgrf_init();
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#endif
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return 0;
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}
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#endif
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