/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3328.h>
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#include <asm/arch/uart.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CRU_BASE 0xFF440000
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#define GRF_BASE 0xFF100000
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#define UART2_BASE 0xFF130000
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#define CRU_MISC_CON 0xff440084
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#define FW_DDR_CON_REG 0xff7c0040
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static struct mm_region rk3328_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0xff000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xff000000UL,
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.phys = 0xff000000UL,
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.size = 0x1000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3328_mem_map;
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/rksdmmc@ff520000",
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[BROM_BOOTSOURCE_SD] = "/rksdmmc@ff500000",
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};
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
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/* We do some SoC one time setting here. */
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/* Disable the ddr secure region setting to make it non-secure */
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rk_setreg(FW_DDR_CON_REG, 0x200);
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/* Enable force to jtag, jtag_tclk/tms iomuxed with sdmmc0_d2/d3 */
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rk_setreg(&grf->soc_con[4], 1 << 12);
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/* HDMI phy clock source select HDMIPHY clock out */
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rk_clrreg(CRU_MISC_CON, 1 << 13);
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/* TODO: ECO version */
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#endif
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return 0;
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}
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#endif
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void board_debug_uart_init(void)
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{
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#ifdef CONFIG_TPL_BUILD
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struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
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struct rk_uart * const uart = (void *)UART2_BASE;
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enum{
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GPIO2A0_SEL_SHIFT = 0,
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GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
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GPIO2A0_UART2_TX_M1 = 1,
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GPIO2A1_SEL_SHIFT = 2,
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GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
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GPIO2A1_UART2_RX_M1 = 1,
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};
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enum {
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IOMUX_SEL_UART2_SHIFT = 0,
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IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
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IOMUX_SEL_UART2_M0 = 0,
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IOMUX_SEL_UART2_M1,
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};
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/* uart_sel_clk default select 24MHz */
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writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
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/* init uart baud rate 1500000 */
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writel(0x83, &uart->lcr);
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writel(0x1, &uart->rbr);
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writel(0x3, &uart->lcr);
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/* Enable early UART2 */
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rk_clrsetreg(&grf->com_iomux,
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IOMUX_SEL_UART2_MASK,
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IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A0_SEL_MASK,
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GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GPIO2A1_SEL_MASK,
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GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
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/* enable FIFO */
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writel(0x1, &uart->sfe);
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#endif
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}
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