// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data rk1808_mux_route_data[] = {
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{
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/* i2c2m0_sda */
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.bank_num = 3,
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.pin = 12,
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.func = 2,
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.route_offset = 0x190,
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.route_val = BIT(16 + 3),
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}, {
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/* i2c2m1_sda */
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.bank_num = 1,
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.pin = 13,
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.func = 2,
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.route_offset = 0x190,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* uart2_rxm0 */
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.bank_num = 4,
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.pin = 3,
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.func = 2,
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.route_offset = 0x190,
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.route_val = BIT(16 + 14) | BIT(16 + 15),
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}, {
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/* uart2_rxm1 */
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.bank_num = 2,
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.pin = 25,
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.func = 2,
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.route_offset = 0x190,
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.route_val = BIT(16 + 14) | BIT(14) | BIT(16 + 15),
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}, {
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/* uart2_rxm2 */
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.bank_num = 3,
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.pin = 4,
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.func = 2,
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.route_offset = 0x190,
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.route_val = BIT(16 + 14) | BIT(16 + 15) | BIT(15),
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},
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};
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static int rk1808_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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regmap = priv->regmap_pmu;
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else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
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regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
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else
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regmap = priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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if (mux_type & IOMUX_WIDTH_4BIT) {
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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} else {
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bit = (pin % 8) * 2;
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mask = 0x3;
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}
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK1808_PULL_PMU_OFFSET 0x10
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#define RK1808_PULL_GRF_OFFSET 0x80
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#define RK1808_PULL_PINS_PER_REG 8
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#define RK1808_PULL_BITS_PER_PIN 2
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#define RK1808_PULL_BANK_STRIDE 16
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static void rk1808_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK1808_PULL_PMU_OFFSET;
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} else {
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*reg = RK1808_PULL_GRF_OFFSET;
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*regmap = priv->regmap_base;
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}
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*reg += ((pin_num / RK1808_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % RK1808_PULL_PINS_PER_REG);
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*bit *= RK1808_PULL_BITS_PER_PIN;
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}
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#define RK1808_DRV_PMU_OFFSET 0x20
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#define RK1808_DRV_GRF_OFFSET 0x140
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#define RK1808_DRV_BITS_PER_PIN 2
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#define RK1808_DRV_PINS_PER_REG 8
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#define RK1808_DRV_BANK_STRIDE 16
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static void rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK1808_DRV_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK1808_DRV_GRF_OFFSET;
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}
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*reg += ((pin_num / RK1808_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK1808_DRV_PINS_PER_REG;
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*bit *= RK1808_DRV_BITS_PER_PIN;
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}
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#define RK1808_SCHMITT_PMU_OFFSET 0x0040
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#define RK1808_SCHMITT_GRF_OFFSET 0x0100
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#define RK1808_SCHMITT_BANK_STRIDE 16
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#define RK1808_SCHMITT_PINS_PER_REG 8
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static int rk1808_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = RK1808_SCHMITT_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK1808_SCHMITT_GRF_OFFSET;
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*reg += (bank->bank_num - 1) * RK1808_SCHMITT_BANK_STRIDE;
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}
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*reg += ((pin_num / RK1808_SCHMITT_PINS_PER_REG) * 4);
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*bit = pin_num % RK1808_SCHMITT_PINS_PER_REG;
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return 0;
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}
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static int rk1808_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk1808_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static int rk1808_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg;
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u32 data;
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u8 bit;
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rk1808_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (strength << bit);
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return regmap_write(regmap, reg, data);
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}
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static int rk1808_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u8 bit;
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u32 data;
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rk1808_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = BIT(bit + 16) | (enable << bit);
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return regmap_write(regmap, reg, data);
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}
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static struct rockchip_pin_bank rk1808_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT),
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PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT),
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};
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static const struct rockchip_pin_ctrl rk1808_pin_ctrl = {
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.pin_banks = rk1808_pin_banks,
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.nr_banks = ARRAY_SIZE(rk1808_pin_banks),
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.nr_pins = 160,
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.iomux_routes = rk1808_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk1808_mux_route_data),
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.grf_mux_offset = 0x0,
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.pmu_mux_offset = 0x0,
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.set_mux = rk1808_set_mux,
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.set_pull = rk1808_set_pull,
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.set_drive = rk1808_set_drive,
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.set_schmitt = rk1808_set_schmitt,
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};
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static const struct udevice_id rk1808_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk1808-pinctrl",
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.data = (ulong)&rk1808_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk1808) = {
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.name = "rockchip_rk1808_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk1808_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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