/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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struct clk_fixed_rate {
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unsigned long fixed_rate;
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};
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#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
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static ulong clk_fixed_rate_get_rate(struct clk *clk)
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{
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if (clk->id != 0)
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return -EINVAL;
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return to_clk_fixed_rate(clk->dev)->fixed_rate;
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}
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const struct clk_ops clk_fixed_rate_ops = {
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.get_rate = clk_fixed_rate_get_rate,
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};
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static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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to_clk_fixed_rate(dev)->fixed_rate = dev_read_u32_default(dev,
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"clock-frequency", 0);
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#endif
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return 0;
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}
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static const struct udevice_id clk_fixed_rate_match[] = {
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{
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.compatible = "fixed-clock",
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(clk_fixed_rate) = {
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.name = "fixed_rate_clock",
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.id = UCLASS_CLK,
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.of_match = clk_fixed_rate_match,
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.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
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.ops = &clk_fixed_rate_ops,
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};
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