/*
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* Rockchip DP PHY driver
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*
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* Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
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* Author: Yakir Yang <ykk@@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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struct rockchip_dp_phy_data {
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u32 grf_reg_offset;
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u8 ref_clk_sel_shift;
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u8 iddq_shift;
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};
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struct rockchip_dp_phy {
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struct device *dev;
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struct regmap *grf;
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struct clk *phy_24m;
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struct reset_control *rst;
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const struct rockchip_dp_phy_data *data;
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};
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static int rockchip_dp_phy_power_on(struct phy *phy)
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{
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struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
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const struct rockchip_dp_phy_data *data = dp->data;
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if (!__clk_is_enabled(dp->phy_24m))
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clk_prepare_enable(dp->phy_24m);
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if (dp->rst) {
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/* EDP 24m clock domain software reset */
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reset_control_assert(dp->rst);
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usleep_range(20, 40);
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reset_control_deassert(dp->rst);
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}
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regmap_write(dp->grf, data->grf_reg_offset,
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0 | BIT(16 + data->iddq_shift));
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return 0;
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}
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static int rockchip_dp_phy_power_off(struct phy *phy)
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{
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struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
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const struct rockchip_dp_phy_data *data = dp->data;
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regmap_write(dp->grf, data->grf_reg_offset,
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BIT(data->iddq_shift) | BIT(16 + data->iddq_shift));
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if (__clk_is_enabled(dp->phy_24m))
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clk_disable_unprepare(dp->phy_24m);
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return 0;
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}
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static const struct phy_ops rockchip_dp_phy_ops = {
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.power_on = rockchip_dp_phy_power_on,
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.power_off = rockchip_dp_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int rockchip_dp_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct phy_provider *phy_provider;
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struct rockchip_dp_phy *dp;
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const struct rockchip_dp_phy_data *data = of_device_get_match_data(dev);
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struct phy *phy;
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int ret;
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if (!np)
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return -ENODEV;
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if (!dev->parent || !dev->parent->of_node)
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return -ENODEV;
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dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
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if (!dp)
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return -ENOMEM;
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dp->dev = dev;
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dp->data = data;
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dp->phy_24m = devm_clk_get(dev, "24m");
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if (IS_ERR(dp->phy_24m)) {
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dev_err(dev, "cannot get clock 24m\n");
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return PTR_ERR(dp->phy_24m);
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}
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ret = clk_set_rate(dp->phy_24m, 24000000);
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if (ret < 0) {
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dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(dp->phy_24m);
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if (ret) {
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dev_err(dev, "failed to enable phy 24m clock: %d\n", ret);
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return ret;
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}
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dp->rst = devm_reset_control_get_optional(dev, "edp_24m");
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if (IS_ERR(dp->rst)) {
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ret = PTR_ERR(dp->rst);
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dev_err(dev, "failed to get reset control: %d\n", ret);
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return ret;
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}
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dp->grf = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(dp->grf)) {
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dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
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return PTR_ERR(dp->grf);
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}
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/* eDP PHY reference clock source from internal clock */
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ret = regmap_write(dp->grf, data->grf_reg_offset,
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BIT(data->ref_clk_sel_shift) |
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BIT(16 + data->ref_clk_sel_shift));
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if (ret) {
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dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
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return ret;
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}
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phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create phy\n");
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return PTR_ERR(phy);
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}
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phy_set_drvdata(phy, dp);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct rockchip_dp_phy_data rk3288_dp_phy_data = {
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.grf_reg_offset = 0x274,
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.ref_clk_sel_shift = 4,
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.iddq_shift = 5,
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};
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static const struct rockchip_dp_phy_data rk3368_dp_phy_data = {
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.grf_reg_offset = 0x410,
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.ref_clk_sel_shift = 0,
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.iddq_shift = 1,
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};
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static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-dp-phy", .data = &rk3288_dp_phy_data },
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{ .compatible = "rockchip,rk3368-dp-phy", .data = &rk3368_dp_phy_data },
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
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static struct platform_driver rockchip_dp_phy_driver = {
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.probe = rockchip_dp_phy_probe,
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.driver = {
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.name = "rockchip-dp-phy",
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.of_match_table = rockchip_dp_phy_dt_ids,
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},
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};
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module_platform_driver(rockchip_dp_phy_driver);
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MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip DP PHY driver");
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MODULE_LICENSE("GPL v2");
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