/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef ADF_TRANSPORT_ACCESS_MACROS_H
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#define ADF_TRANSPORT_ACCESS_MACROS_H
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#include "adf_accel_devices.h"
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#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
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#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
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#define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF
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#define ADF_RING_CSR_RING_CONFIG 0x000
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#define ADF_RING_CSR_RING_LBASE 0x040
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#define ADF_RING_CSR_RING_UBASE 0x080
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#define ADF_RING_CSR_RING_HEAD 0x0C0
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#define ADF_RING_CSR_RING_TAIL 0x100
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#define ADF_RING_CSR_E_STAT 0x14C
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#define ADF_RING_CSR_INT_FLAG 0x170
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#define ADF_RING_CSR_INT_SRCSEL 0x174
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#define ADF_RING_CSR_INT_SRCSEL_2 0x178
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#define ADF_RING_CSR_INT_COL_EN 0x17C
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#define ADF_RING_CSR_INT_COL_CTL 0x180
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#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
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#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
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#define ADF_RING_BUNDLE_SIZE 0x1000
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#define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
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#define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
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#define ADF_COALESCING_MIN_TIME 0x1FF
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#define ADF_COALESCING_MAX_TIME 0xFFFFF
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#define ADF_COALESCING_DEF_TIME 0x27FF
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#define ADF_RING_NEAR_WATERMARK_512 0x08
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#define ADF_RING_NEAR_WATERMARK_0 0x00
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#define ADF_RING_EMPTY_SIG 0x7F7F7F7F
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/* Valid internal ring size values */
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#define ADF_RING_SIZE_128 0x01
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#define ADF_RING_SIZE_256 0x02
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#define ADF_RING_SIZE_512 0x03
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#define ADF_RING_SIZE_4K 0x06
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#define ADF_RING_SIZE_16K 0x08
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#define ADF_RING_SIZE_4M 0x10
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#define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
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#define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
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#define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
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/* Valid internal msg size values */
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#define ADF_MSG_SIZE_32 0x01
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#define ADF_MSG_SIZE_64 0x02
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#define ADF_MSG_SIZE_128 0x04
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#define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
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#define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
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/* Size to bytes conversion macros for ring and msg size values */
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#define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
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#define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
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#define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
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#define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
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/* Minimum ring bufer size for memory allocation */
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#define ADF_RING_SIZE_BYTES_MIN(SIZE) \
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((SIZE < ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K)) ? \
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ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K) : SIZE)
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#define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
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#define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
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SIZE) & ~0x4)
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/* Max outstanding requests */
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#define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
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((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
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#define BUILD_RING_CONFIG(size) \
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((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
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| (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
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| size)
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#define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
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((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \
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| (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
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| size)
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#define BUILD_RING_BASE_ADDR(addr, size) \
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((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
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#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_HEAD + (ring << 2))
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#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_TAIL + (ring << 2))
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#define READ_CSR_E_STAT(csr_base_addr, bank) \
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ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_E_STAT)
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#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
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#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
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do { \
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uint32_t l_base = 0, u_base = 0; \
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l_base = (uint32_t)(value & 0xFFFFFFFF); \
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u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
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} while (0)
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#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_HEAD + (ring << 2), value)
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#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_RING_TAIL + (ring << 2), value)
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#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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ADF_RING_CSR_INT_FLAG, value)
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#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
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do { \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
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} while (0)
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#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_INT_COL_EN, value)
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#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_INT_COL_CTL, \
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ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
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#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
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ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
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ADF_RING_CSR_INT_FLAG_AND_COL, value)
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#endif
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