/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_BOOK3S_32_HASH_H
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#define _ASM_POWERPC_BOOK3S_32_HASH_H
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#ifdef __KERNEL__
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/*
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* The "classic" 32-bit implementation of the PowerPC MMU uses a hash
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* table containing PTEs, together with a set of 16 segment registers,
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* to define the virtual to physical address mapping.
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*
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* We use the hash table as an extended TLB, i.e. a cache of currently
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* active mappings. We maintain a two-level page table tree, much
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* like that used by the i386, for the sake of the Linux memory
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* management code. Low-level assembler code in hash_low_32.S
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* (procedure hash_page) is responsible for extracting ptes from the
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* tree and putting them into the hash table when necessary, and
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* updating the accessed and modified bits in the page table tree.
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*/
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#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
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#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
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#define _PAGE_USER 0x004 /* usermode access allowed */
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#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
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#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_RW 0x400 /* software: user write access allowed */
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#define _PAGE_SPECIAL 0x800 /* software: Special page */
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#ifdef CONFIG_PTE_64BIT
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/* We never clear the high word of the pte */
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#define _PTE_NONE_MASK (0xffffffff00000000ULL | _PAGE_HASHPTE)
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#else
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#define _PTE_NONE_MASK _PAGE_HASHPTE
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#endif
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_BOOK3S_32_HASH_H */
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