Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
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DESCRIPTION
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The PAMU is an I/O MMU that provides device-to-memory access control and
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address translation capabilities.
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Required properties:
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- compatible : <string>
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First entry is a version-specific string, such as
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"fsl,pamu-v1.0". The second is "fsl,pamu".
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- ranges : <prop-encoded-array>
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A standard property. Utilized to describe the memory mapped
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I/O space utilized by the controller. The size should
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be set to the total size of the register space of all
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physically present PAMU controllers. For example, for
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PAMU v1.0, on an SOC that has five PAMU devices, the size
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is 0x5000.
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- interrupts : <prop-encoded-array>
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Interrupt mappings. The first tuple is the normal PAMU
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interrupt, used for reporting access violations. The second
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is for PAMU hardware errors, such as PAMU operation errors
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and ECC errors.
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- #address-cells: <u32>
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A standard property.
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- #size-cells : <u32>
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A standard property.
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Optional properties:
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- reg : <prop-encoded-array>
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A standard property. It represents the CCSR registers of
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all child PAMUs combined. Include it to provide support
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for legacy drivers.
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- fsl,portid-mapping : <u32>
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The Coherency Subdomain ID Port Mapping Registers and
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Snoop ID Port Mapping registers, which are part of the
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CoreNet Coherency fabric (CCF), provide a CoreNet
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Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
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functions. Certain bits from these registers should be
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set if PAMUs should be snooped. This property defines
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a bitmask which selects the bits that should be set if
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PAMUs should be snooped.
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Child nodes:
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Each child node represents one PAMU controller. Each SOC device that is
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connected to a specific PAMU device should have a "fsl,pamu-phandle" property
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that links to the corresponding specific child PAMU controller.
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- reg : <prop-encoded-array>
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A standard property. Specifies the physical address and
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length (relative to the parent 'ranges' property) of this
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PAMU controller's configuration registers. The size should
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be set to the size of this PAMU controllers's register space.
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For PAMU v1.0, this size is 0x1000.
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- fsl,primary-cache-geometry
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: <prop-encoded-array>
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Two cells that specify the geometry of the primary PAMU
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cache. The first is the number of cache lines, and the
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second is the number of "ways". For direct-mapped caches,
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specify a value of 1.
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- fsl,secondary-cache-geometry
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: <prop-encoded-array>
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Two cells that specify the geometry of the secondary PAMU
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cache. The first is the number of cache lines, and the
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second is the number of "ways". For direct-mapped caches,
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specify a value of 1.
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Device nodes:
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Devices that have LIODNs need to specify links to the parent PAMU controller
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(the actual PAMU controller that this device is connected to) and a pointer to
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the LIODN register, if applicable.
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- fsl,iommu-parent
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: <phandle>
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Phandle to the single, specific PAMU controller node to which
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this device is connect. The PAMU topology is represented in
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the device tree to assist code that dynamically determines the
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best LIODN values to minimize PAMU cache thrashing.
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- fsl,liodn-reg : <prop-encoded-array>
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Two cells that specify the location of the LIODN register
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for this device. Required for devices that have a single
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LIODN. The first cell is a phandle to a node that contains
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the registers where the LIODN is to be set. The second is
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the offset from the first "reg" resource of the node where
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the specific LIODN register is located.
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Example:
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x5000>;
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ranges = <0 0x20000 0x5000>;
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fsl,portid-mapping = <0xf80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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pamu0: pamu@0 {
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reg = <0 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu1: pamu@1000 {
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reg = <0x1000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu2: pamu@2000 {
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reg = <0x2000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu3: pamu@3000 {
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reg = <0x3000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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pamu4: pamu@4000 {
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reg = <0x4000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <128 2>;
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};
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};
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guts: global-utilities@e0000 {
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compatible = "fsl,qoriq-device-config-1.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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#sleep-cells = <1>;
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fsl,liodn-bits = <12>;
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};
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/include/ "qoriq-dma-0.dtsi"
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dma@100300 {
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
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};
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