OpenRISC Generic SoC
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====================
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Boards and FPGA SoC's which support the OpenRISC standard platform. The
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platform essentially follows the conventions of the OpenRISC architecture
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specification, however some aspects, such as the boot protocol have been defined
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by the Linux port.
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Required properties
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-------------------
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- compatible: Must include "opencores,or1ksim"
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CPU nodes:
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----------
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A "cpus" node is required. Required properties:
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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A CPU sub-node is also required for at least CPU 0. Since the topology may
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be probed via CPS, it is not necessary to specify secondary CPUs. Required
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properties:
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- compatible: Must be "opencores,or1200-rtlsvn481".
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- reg: CPU number.
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- clock-frequency: The CPU clock frequency in Hz.
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Example:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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};
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};
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Boot protocol
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-------------
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The bootloader may pass the following arguments to the kernel:
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- r3: address of a flattened device-tree blob or 0x0.
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