Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
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---------------------------------------------------------
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Required properties:
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- compatible : Should be:
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- "xlnx,zynq-can-1.0" for Zynq CAN controllers
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- "xlnx,axi-can-1.00.a" for Axi CAN controllers
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- "xlnx,canfd-1.0" for CAN FD controllers
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- reg : Physical base address and size of the controller
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registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- clock-names : List of input clock names
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- "can_clk", "pclk" (For CANPS),
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- "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD).
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(See clock bindings for details).
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- clocks : Clock phandles (see clock bindings for details).
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- tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
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- rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
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sequential Rx mode).
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- tx-mailbox-count : Can Tx mailbox buffer count (CAN FD).
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- rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx
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mode).
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Example:
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For Zynq CANPS Dts file:
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zynq_can_0: can@e0008000 {
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compatible = "xlnx,zynq-can-1.0";
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clocks = <&clkc 19>, <&clkc 36>;
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clock-names = "can_clk", "pclk";
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reg = <0xe0008000 0x1000>;
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interrupts = <0 28 4>;
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interrupt-parent = <&intc>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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For Axi CAN Dts file:
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axi_can_0: axi-can@40000000 {
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compatible = "xlnx,axi-can-1.00.a";
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clocks = <&clkc 0>, <&clkc 1>;
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clock-names = "can_clk","s_axi_aclk" ;
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reg = <0x40000000 0x10000>;
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interrupt-parent = <&intc>;
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interrupts = <0 59 1>;
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tx-fifo-depth = <0x40>;
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rx-fifo-depth = <0x40>;
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};
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For CAN FD Dts file:
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canfd_0: canfd@40000000 {
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compatible = "xlnx,canfd-1.0";
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clocks = <&clkc 0>, <&clkc 1>;
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clock-names = "can_clk", "s_axi_aclk";
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reg = <0x40000000 0x2000>;
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interrupt-parent = <&intc>;
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interrupts = <0 59 1>;
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tx-mailbox-count = <0x20>;
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rx-fifo-depth = <0x20>;
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};
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