Rockchip MIPI CSI HOST
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================================
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Required properties:
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- compatible: must be one of:
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"rockchip,rk1808-mipi-csi".
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- reg: Represent the physical address range of the controller.
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- interrupts: Represent the controller's interrupt to the CPU(s).
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- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
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described in [1].
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- resets : phandle to the reset of MIPI CSI APB Clock.
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- reset-names : should be "apb".
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- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
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- #address-cells: Should be <1>.
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- #size-cells: Should be <0>.
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- ports: contain a port node with endpoint definitions as defined in [2].
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For vopb,set the reg = <0> and set the reg = <1> for vopl.
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Optional properties
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- clocks, clock-names:
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phandle to the SNPS-PHY config clock, name should be "phy_cfg".
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phandle to the SNPS-PHY PLL reference clock, name should be "ref".
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phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
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phandle to the h2p bridge clock, name should be "h2p".
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- phys: phandle to Non-SNPS PHY node
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- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
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attribute, provides phandle to MIPI PHY node
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- rockchip,dual-channel: for dual-channel panel, if not, don't configure
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- rockchip,lane-rate: manually configure lane-rate, not necessary.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/media/video-interfaces.txt
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[3] Documentation/devicetree/bindings/reset/reset.txt
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Example:
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For Rockchip RK1808:
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csi: csi@ffb20000 {
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compatible = "rockchip,rk1808-mipi-csi";
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clocks = <&cru PCLK_MIPI_CSI0>, <&mipi_dphy>;
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clock-names = "pclk", "hs_clk";
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phys = <&mipi_dphy>;
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phy-names = "mipi_dphy";
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resets = <&cru SRST_MIPICSI>;
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reset-names = "apb";
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...
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ports {
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port {
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csi_in_vop: endpoint {
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remote-endpoint = <&vop_out_csi>;
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};
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};
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};
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};
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