Qualcomm adreno/snapdragon MDP5 display controller
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Description:
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This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
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encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
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controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
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MDSS:
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Required properties:
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- compatible:
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* "qcom,mdss" - MDSS
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- reg: Physical base address and length of the controller's registers.
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- reg-names: The names of register regions. The following regions are required:
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* "mdss_phys"
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* "vbif_phys"
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- interrupts: The interrupt signal from MDSS.
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- power-domains: a power domain consumer specifier according to
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Documentation/devicetree/bindings/power/power_domain.txt
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- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required.
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* "iface"
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* "bus"
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* "vsync"
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- #address-cells: number of address cells for the MDSS children. Should be 1.
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- #size-cells: Should be 1.
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- ranges: parent bus address space is the same as the child bus address space.
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Optional properties:
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- clock-names: the following clocks are optional:
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* "lut"
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MDP5:
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Required properties:
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- compatible:
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* "qcom,mdp5" - MDP5
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- reg: Physical base address and length of the controller's registers.
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- reg-names: The names of register regions. The following regions are required:
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* "mdp_phys"
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- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
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- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required.
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- * "bus"
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- * "iface"
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- * "core"
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- * "vsync"
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- ports: contains the list of output ports from MDP. These connect to interfaces
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that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
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special case since it is a part of the MDP block itself).
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Each output port contains an endpoint that describes how it is connected to an
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external interface. These are described by the standard properties documented
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here:
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Documentation/devicetree/bindings/graph.txt
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Documentation/devicetree/bindings/media/video-interfaces.txt
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The availability of output ports can vary across SoC revisions:
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For MSM8974 and APQ8084:
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Port 0 -> MDP_INTF0 (eDP)
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Port 1 -> MDP_INTF1 (DSI1)
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Port 2 -> MDP_INTF2 (DSI2)
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Port 3 -> MDP_INTF3 (HDMI)
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For MSM8916:
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Port 0 -> MDP_INTF1 (DSI1)
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For MSM8994 and MSM8996:
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Port 0 -> MDP_INTF1 (DSI1)
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Port 1 -> MDP_INTF2 (DSI2)
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Port 2 -> MDP_INTF3 (HDMI)
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Optional properties:
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- clock-names: the following clocks are optional:
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* "lut"
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Example:
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/ {
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...
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mdss: mdss@1a00000 {
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compatible = "qcom,mdss";
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reg = <0x1a00000 0x1000>,
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<0x1ac8000 0x3000>;
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reg-names = "mdss_phys", "vbif_phys";
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power-domains = <&gcc MDSS_GDSC>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"vsync"
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interrupts = <0 72 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mdp: mdp@1a01000 {
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compatible = "qcom,mdp5";
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reg = <0x1a01000 0x90000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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interrupts = <0 0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdp5_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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dsi0: dsi@1a98000 {
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...
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ports {
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...
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&mdp5_intf1_out>;
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};
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};
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...
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};
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...
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};
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dsi_phy0: dsi-phy@1a98300 {
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...
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};
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};
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};
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