Mediatek HDMI Encoder
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=====================
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The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
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its parallel input.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi".
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
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- phys: phandle link to the HDMI PHY node.
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See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
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- phy-names: must contain "hdmi"
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- mediatek,syscon-hdmi: phandle link and register offset to the system
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configuration registers. For mt8173 this must be offset 0x900 into the
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MMSYS_CONFIG region: <&mmsys 0x900>.
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- ports: A node containing input and output port nodes with endpoint
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definitions as documented in Documentation/devicetree/bindings/graph.txt.
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- port@0: The input port in the ports node should be connected to a DPI output
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port.
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- port@1: The output port in the ports node should be connected to the input
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port of a connector node that contains a ddc-i2c-bus property, or to the
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input port of an attached bridge chip, such as a SlimPort transmitter.
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HDMI CEC
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========
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The HDMI CEC controller handles hotplug detection and CEC communication.
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Required properties:
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- compatible: Should be "mediatek,<chip>-cec"
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clock
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HDMI DDC
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========
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The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
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The Mediatek's I2C controller is used to interface with I2C devices.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi-ddc"
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- reg: Physical base address and length of the controller's registers
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- clocks: device clock
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- clock-names: Should be "ddc-i2c".
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HDMI PHY
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========
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The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
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output and drives the HDMI pads.
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Required properties:
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- compatible: "mediatek,<chip>-hdmi-phy"
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- reg: Physical base address and length of the module's registers
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- clocks: PLL reference clock
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- clock-names: must contain "pll_ref"
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- clock-output-names: must be "hdmitx_dig_cts" on mt8173
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- #phy-cells: must be <0>
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- #clock-cells: must be <0>
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Optional properties:
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- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
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- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
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Example:
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cec: cec@10013000 {
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compatible = "mediatek,mt8173-cec";
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reg = <0 0x10013000 0 0xbc>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_CEC>;
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};
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hdmi_phy: hdmi-phy@10209100 {
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compatible = "mediatek,mt8173-hdmi-phy";
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reg = <0 0x10209100 0 0x24>;
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clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
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clock-names = "pll_ref";
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clock-output-names = "hdmitx_dig_cts";
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mediatek,ibias = <0xa>;
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mediatek,ibias_up = <0x1c>;
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#clock-cells = <0>;
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#phy-cells = <0>;
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};
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hdmi_ddc0: i2c@11012000 {
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compatible = "mediatek,mt8173-hdmi-ddc";
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reg = <0 0x11012000 0 0x1c>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_I2C5>;
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clock-names = "ddc-i2c";
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};
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hdmi0: hdmi@14025000 {
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compatible = "mediatek,mt8173-hdmi";
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reg = <0 0x14025000 0 0x400>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
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<&mmsys CLK_MM_HDMI_PLLCK>,
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<&mmsys CLK_MM_HDMI_AUDIO>,
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<&mmsys CLK_MM_HDMI_SPDIF>;
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clock-names = "pixel", "pll", "bclk", "spdif";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmi_pin>;
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phys = <&hdmi_phy>;
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phy-names = "hdmi";
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mediatek,syscon-hdmi = <&mmsys 0x900>;
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assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
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assigned-clock-parents = <&hdmi_phy>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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hdmi0_in: endpoint {
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remote-endpoint = <&dpi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi0_out: endpoint {
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remote-endpoint = <&hdmi_con_in>;
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};
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};
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};
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};
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connector {
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compatible = "hdmi-connector";
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type = "a";
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ddc-i2c-bus = <&hdmiddc0>;
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port {
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hdmi_con_in: endpoint {
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remote-endpoint = <&hdmi0_out>;
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};
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};
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};
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