Device-Tree bindings for Samsung SoC display controller (FIMD)
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FIMD (Fully Interactive Mobile Display) is the Display Controller for the
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Samsung series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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Required properties:
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- compatible: value should be one of the following
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"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
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"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
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"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
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"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
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"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
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"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
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"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
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- reg: physical base address and length of the FIMD registers set.
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- interrupts: should contain a list of all FIMD IP block interrupts in the
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order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
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format depends on the interrupt controller used.
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- interrupt-names: should contain the interrupt names: "fifo", "vsync",
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"lcd_sys", in the same order as they were listed in the interrupts
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property.
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- pinctrl-0: pin control group to be used for this controller.
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- pinctrl-names: must contain a "default" entry.
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- clocks: must include clock specifiers corresponding to entries in the
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clock-names property.
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- clock-names: list of clock names sorted in the same order as the clocks
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property. Must contain "sclk_fimd" and "fimd".
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Optional Properties:
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- power-domains: a phandle to FIMD power domain node.
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- samsung,invert-vden: video enable signal is inverted
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- samsung,invert-vclk: video clock signal is inverted
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- display-timings: timing settings for FIMD, as described in document [1].
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Can be used in case timings cannot be provided otherwise
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or to override timings provided by the panel.
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- samsung,sysreg: handle to syscon used to control the system registers
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- i80-if-timings: timing configuration for lcd i80 interface support.
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- cs-setup: clock cycles for the active period of address signal is enabled
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until chip select is enabled.
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If not specified, the default value(0) will be used.
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- wr-setup: clock cycles for the active period of CS signal is enabled until
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write signal is enabled.
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If not specified, the default value(0) will be used.
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- wr-active: clock cycles for the active period of CS is enabled.
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If not specified, the default value(1) will be used.
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- wr-hold: clock cycles for the active period of CS is disabled until write
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signal is disabled.
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If not specified, the default value(0) will be used.
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The parameters are defined as:
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VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
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: : : : :
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Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
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| cs-setup+1 | : : :
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|<---------->| : : :
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Chip Select ???????????????|____________:____________:____________|??
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| wr-setup+1 | | wr-hold+1 |
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|<---------->| |<---------->|
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Write Enable ????????????????????????????|____________|???????????????
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| wr-active+1|
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|<---------->|
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Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
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The device node can contain 'port' child nodes according to the bindings defined
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in [2]. The following are properties specific to those nodes:
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- reg: (required) port index, can be:
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0 - for CAMIF0 input,
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1 - for CAMIF1 input,
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2 - for CAMIF2 input,
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3 - for parallel output,
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4 - for write-back interface
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[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
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[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
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Example:
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SoC specific DT entry:
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fimd@11c00000 {
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compatible = "samsung,exynos4210-fimd";
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interrupt-parent = <&combiner>;
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reg = <0x11c00000 0x20000>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <11 0>, <11 1>, <11 2>;
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clocks = <&clock 140>, <&clock 283>;
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clock-names = "sclk_fimd", "fimd";
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power-domains = <&pd_lcd0>;
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status = "disabled";
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};
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Board specific DT entry:
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fimd@11c00000 {
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pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
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pinctrl-names = "default";
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status = "okay";
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};
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