Synopsys DesignWare HDMI TX Encoder
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This document defines device tree properties for the Synopsys DesignWare HDMI
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TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
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specification by itself but is meant to be referenced by platform-specific
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device tree bindings.
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When referenced from platform device tree bindings the properties defined in
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this document are defined as follows. The platform device tree bindings are
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responsible for defining whether each property is required or optional.
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- reg: Memory mapped base address and length of the DWC HDMI TX registers.
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- reg-io-width: Width of the registers specified by the reg property. The
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value is expressed in bytes and must be equal to 1 or 4 if specified. The
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register width defaults to 1 if the property is not present.
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- interrupts: Reference to the DWC HDMI TX interrupt.
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- clocks: References to all the clocks specified in the clock-names property
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as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
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- clock-names: The DWC HDMI TX uses the following clocks.
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- "iahb" is the bus clock for either AHB and APB (mandatory).
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- "isfr" is the internal register configuration clock (mandatory).
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- "cec" is the HDMI CEC controller main clock (optional).
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- ports: The connectivity of the DWC HDMI TX with the rest of the system is
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expressed in using ports as specified in the device graph bindings defined
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in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
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is platform-specific.
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