* Rockchip DMC(Dynamic Memory Controller) device
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Required properties:
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- compatible: Should be one of the following.
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- "rockchip,px30-dmc" - for PX30 SoCs.
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- "rockchip,rk1808-dmc" - for RK1808 SoCs.
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- "rockchip,rk3128-dmc" - for RK3128 SoCs.
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- "rockchip,rk3228-dmc" - for RK3228 SoCs.
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- "rockchip,rk3288-dmc" - for RK3288 SoCs.
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- "rockchip,rk3308-dmc" - for RK3308 SoCs.
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- "rockchip,rk3328-dmc" - for RK3328 SoCs.
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- "rockchip,rk3368-dmc" - for RK3368 SoCs.
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- "rockchip,rk3399-dmc" - for RK3399 SoCs.
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- "rockchip,rk3528-dmc" - for RK3528 SoCs.
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- "rockchip,rk3568-dmc" - for RK3568 SoCs.
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- "rockchip,rv1126-dmc" - for RV1126 SoCs.
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- devfreq-events: Node to get DDR loading, Refer to
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Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
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- interrupts: The interrupt number to the CPU. The interrupt specifier format
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depends on the interrupt controller. It should be DCF interrupts,
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when DDR dvfs finish, it will happen.
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- clocks: Phandles for clock specified in "clock-names" property
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- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon";
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- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
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for details.
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- center-supply: DMC supply node.
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- status: Marks the node enabled/disabled.
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Optional properties:
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- ddr_timing: DDR timing need to pass to arm trust firmware
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- upthreshold: The upthreshold to simpleondeamnd policy
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- downdifferential: The downdifferential to simpleondeamnd policy
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- vop-bw-dmc-freq: The property is an array of 3-tuples items, and
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each item consists of bandwidth and frequency like
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<min-bandwidth max-bandwidth frequency>.
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min-bandwidth: minimum ddr bandwidth in Mbyte/sec.
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max-bandwidth: maximum ddr bandwidth in Mbyte/sec.
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frequency: ddr frequency in KHz.
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- #cooling-cells: This property indicates dmc can work as a cooling device
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- ddr_power_model: Sets power model parameters.
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- dynamic-power-coefficient: A u32 value that represents the running time dynamic
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power coefficient in units of mW/MHz/uVolt^2. The coefficient can either be
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calculated from power measurements or derived by analysis.
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- static-power-coefficient: A u32 value that represents the static power
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coefficient.
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- ts: An array containing coefficients for the temperature scaling factor.
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Used as : tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0], where T = temperature
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- thermal-zone: A string identifying the thermal zone used for the dmc
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Example:
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <21>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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dram_dll_dis_freq = <300>;
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phy_dll_dis_freq = <125>;
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ddr3_odt_dis_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_odt = <PHY_DRV_ODT_240>;
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lpddr3_odt_dis_freq = <333>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
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phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
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phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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lpddr4_odt_dis_freq = <333>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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};
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dmc_opp_table: dmc_opp_table {
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compatible = "operating-points-v2";
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opp00 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <900000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <666000000>;
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opp-microvolt = <900000>;
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};
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};
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dmc: dmc {
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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ddr_timing = <&ddr_timing>;
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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upthreshold = <15>;
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downdifferential = <10>;
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#cooling-cells = <2>;
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ddr_power_model: ddr_power_model {
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dynamic-power-coefficient = <120>;
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static-power-coefficient = <300>;
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ts = <32000 4700 (-80) 2>;
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thermal-zone = "soc-thermal";
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}
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status = "disabled";
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};
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