QCOM Idle States for cpuidle driver
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ARM provides idle-state node to define the cpuidle states, as defined in [1].
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cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
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states. Idle states have different enter/exit latency and residency values.
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The idle states supported by the QCOM SoC are defined as -
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* Standby
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* Retention
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* Standalone Power Collapse (Standalone PC or SPC)
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* Power Collapse (PC)
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Standby: Standby does a little more in addition to architectural clock gating.
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When the WFI instruction is executed the ARM core would gate its internal
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clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
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trigger to execute the SPM state machine. The SPM state machine waits for the
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interrupt to trigger the core back in to active. This triggers the cache
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hierarchy to enter standby states, when all cpus are idle. An interrupt brings
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the SPM state machine out of its wait, the next step is to ensure that the
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cache hierarchy is also out of standby, and then the cpu is allowed to resume
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execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
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driver and is not defined in the DT. The SPM state machine should be
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configured to execute this state by default and after executing every other
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state below.
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Retention: Retention is a low power state where the core is clock gated and
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the memory and the registers associated with the core are retained. The
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voltage may be reduced to the minimum value needed to keep the processor
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registers active. The SPM should be configured to execute the retention
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sequence and would wait for interrupt, before restoring the cpu to execution
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state. Retention may have a slightly higher latency than Standby.
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Standalone PC: A cpu can power down and warmboot if there is a sufficient time
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between the time it enters idle and the next known wake up. SPC mode is used
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to indicate a core entering a power down state without consulting any other
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cpu or the system resources. This helps save power only on that core. The SPM
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sequence for this idle state is programmed to power down the supply to the
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core, wait for the interrupt, restore power to the core, and ensure the
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system state including cache hierarchy is ready before allowing core to
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resume. Applying power and resetting the core causes the core to warmboot
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back into Elevation Level (EL) which trampolines the control back to the
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kernel. Entering a power down state for the cpu, needs to be done by trapping
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into a EL. Failing to do so, would result in a crash enforced by the warm boot
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code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
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be flushed in s/w, before powering down the core.
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Power Collapse: This state is similar to the SPC mode, but distinguishes
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itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
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modes. In a hierarchical power domain SoC, this means L2 and other caches can
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be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
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voltages reduced, provided all cpus enter this state. Since the span of low
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power modes possible at this state is vast, the exit latency and the residency
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of this low power mode would be considered high even though at a cpu level,
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this essentially is cpu power down. The SPM in this state also may handshake
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with the Resource power manager (RPM) processor in the SoC to indicate a
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complete application processor subsystem shut down.
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The idle-state for QCOM SoCs are distinguished by the compatible property of
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the idle-states device node.
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The devicetree representation of the idle state should be -
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Required properties:
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- compatible: Must be one of -
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"qcom,idle-state-ret",
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"qcom,idle-state-spc",
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"qcom,idle-state-pc",
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and "arm,idle-state".
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Other required and optional properties are specified in [1].
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Example:
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idle-states {
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CPU_SPC: spc {
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compatible = "qcom,idle-state-spc", "arm,idle-state";
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entry-latency-us = <150>;
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exit-latency-us = <200>;
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min-residency-us = <2000>;
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};
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};
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[1]. Documentation/devicetree/bindings/arm/idle-states.txt
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