Freescale Vybrid Miscellaneous System Control - Interrupt Router
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The MSCM IP contains multiple sub modules, this binding describes the second
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block of registers which control the interrupt router. The interrupt router
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allows to configure the recipient of each peripheral interrupt. Furthermore
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it controls the directed processor interrupts. The module is available in all
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Vybrid SoC's but is only really useful in dual core configurations (VF6xx
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which comes with a Cortex-A5/Cortex-M4 combination).
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Required properties:
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- compatible: "fsl,vf610-mscm-ir"
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- reg: the register range of the MSCM Interrupt Router
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- fsl,cpucfg: The handle to the MSCM CPU configuration node, required
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to get the current CPU ID
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- interrupt-controller: Identifies the node as an interrupt controller
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- #interrupt-cells: Two cells, interrupt number and cells.
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The hardware interrupt number according to interrupt
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assignment of the interrupt router is required.
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Flags get passed only when using GIC as parent. Flags
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encoding as documented by the GIC bindings.
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Example:
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mscm_ir: interrupt-controller@40001800 {
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compatible = "fsl,vf610-mscm-ir";
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reg = <0x40001800 0x400>;
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fsl,cpucfg = <&mscm_cpucfg>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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}
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