// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip PCIE3.0 phy driver
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*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <generic-phy.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <regmap.h>
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#include <reset-uclass.h>
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/* Register for RK3568 */
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#define GRF_PCIE30PHY_RK3568_CON1 0x4
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#define GRF_PCIE30PHY_RK3568_CON4 0x10
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#define GRF_PCIE30PHY_RK3568_CON6 0x18
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#define GRF_PCIE30PHY_RK3568_CON9 0x24
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#define GRF_PCIE30PHY_RK3568_STATUS0 0x80
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#define RK3568_SRAM_INIT_DONE(reg) (reg & BIT(14))
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/* Register for RK3588 */
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#define PHP_GRF_PCIESEL_CON 0x100
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
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#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
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#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
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/*
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* pcie30_phy_mode[2:0]
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* bit2: aggregation
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* bit1: bifurcation for port 1
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* bit0: bifurcation for port 0
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*/
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#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
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#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
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#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
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#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
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struct rockchip_p3phy_ops;
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struct rockchip_p3phy_priv {
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const struct rockchip_p3phy_ops *ops;
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struct clk_bulk clks;
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void __iomem *mmio;
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int mode;
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struct regmap *phy_grf;
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struct regmap *pipe_grf;
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struct reset_ctl p30phy;
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bool is_bifurcation;
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/* pcie30_phymode: Aggregation, Bifurcation */
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int pcie30_phymode;
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};
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struct rockchip_p3phy_ops {
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int (*phy_init)(struct rockchip_p3phy_priv *priv);
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};
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static const u16 phy_fw[] = {
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#include "phy-rockchip-snps-pcie3.fw"
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};
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static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
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{
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int i, ret = 0;
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u32 reg;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
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(0x1 << 15) | (0x1 << 31));
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/* Set bifurcation if needed */
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if (priv->is_bifurcation) {
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON6,
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0x1 | (0xf << 16));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON1,
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(0x1 << 15) | (0x1 << 31));
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
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(0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
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(0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
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reset_deassert(&priv->p30phy);
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udelay(5);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_RK3568_STATUS0,
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reg, RK3568_SRAM_INIT_DONE(reg),
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0, 500);
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if (ret) {
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pr_err("%s: lock failed 0x%x, check refclk and power\n",
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__func__, reg);
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return -ETIMEDOUT;
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}
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
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(0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
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for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
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writel(phy_fw[i], priv->mmio + (i<<2));
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printf("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON9,
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(0x0 << 8) | (0x3 << (8 + 16)));
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_RK3568_CON4,
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(0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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udelay(10);
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return 0;
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}
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static const struct rockchip_p3phy_ops rk3568_ops = {
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.phy_init = &rockchip_p3phy_rk3568_init,
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};
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static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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{
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u32 reg;
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u32 timeout;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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(0x1 << 8) | (0x1 << 24));
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/* Select correct pcie30_phymode */
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if (priv->pcie30_phymode > 4)
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priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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(0x7<<16) | priv->pcie30_phymode);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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reg = priv->pcie30_phymode & 3;
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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(reg << 16) | reg);
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timeout = 500;
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while (timeout--) {
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regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_STATUS1, ®);
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if (reg & 0x1)
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break;
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udelay(1);
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}
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if (timeout <= 0) {
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pr_err("%s: phy0 lock failed, check input refclk and power supply\n", __func__);
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return -ETIMEDOUT;
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}
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timeout = 500;
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while (timeout--) {
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regmap_read(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_STATUS1, ®);
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if (reg & 0x1)
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break;
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udelay(1);
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}
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if (timeout <= 0) {
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pr_err("%s: phy1 lock failed, check input refclk and power supply\n", __func__);
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return -ETIMEDOUT;
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}
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reset_deassert(&priv->p30phy);
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udelay(5);
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return 0;
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}
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static const struct rockchip_p3phy_ops rk3588_ops = {
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.phy_init = &rockchip_p3phy_rk3588_init,
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};
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static int rochchip_p3phy_init(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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int ret;
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ret = clk_enable_bulk(&priv->clks);
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if (ret) {
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pr_err("failed to enable clks (ret=%d)\n", ret);
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return ret;
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}
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reset_assert(&priv->p30phy);
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udelay(1);
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if (priv->ops->phy_init) {
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ret = priv->ops->phy_init(priv);
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if (ret) {
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clk_disable_bulk(&priv->clks);
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return ret;
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}
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}
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return 0;
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}
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static int rochchip_p3phy_exit(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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clk_disable_bulk(&priv->clks);
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reset_assert(&priv->p30phy);
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return 0;
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}
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static int rockchip_p3phy_probe(struct udevice *dev)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
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dev_get_driver_data(dev);
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struct udevice *syscon;
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int ret;
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priv->mmio = (void __iomem *)dev_read_addr(dev);
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if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->ops = (struct rockchip_p3phy_ops *)dev_get_driver_data(dev);
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if (!priv->ops) {
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dev_err(dev, "no of match data provided\n");
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return -EINVAL;
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}
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"rockchip,phy-grf", &syscon);
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if (ret) {
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pr_err("unable to find syscon device for rockchip,phy-grf\n");
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return ret;
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}
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priv->phy_grf = syscon_get_regmap(syscon);
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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return PTR_ERR(priv->phy_grf);
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}
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dev_dbg(priv->dev, "phy_grf is 0x%llx\n", priv->phy_grf->base);
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ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"rockchip,pipe-grf", &syscon);
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if (ret) {
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/* It's optional, rk3568 doesn't need it */
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priv->pipe_grf = NULL;
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pr_err("unable to get syscon device for rockchip,pipe-grf\n");
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goto skip_pipe_grf;
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}
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priv->pipe_grf = syscon_get_regmap(syscon);
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if (IS_ERR(priv->pipe_grf))
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dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
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priv->pcie30_phymode = dev_read_u32_default(dev, "rockchip,pcie30-phymode", PHY_MODE_PCIE_AGGREGATION);
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skip_pipe_grf:
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ret = reset_get_by_name(dev, "phy", &priv->p30phy);
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if (ret) {
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dev_err(dev, "no phy reset control specified\n");
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return ret;
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}
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if (ret) {
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dev_err(dev, "Can't get clock: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int rockchip_p3phy_configure(struct phy *phy, union phy_configure_opts *opts)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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priv->is_bifurcation = opts->pcie.is_bifurcation;
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return 0;
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}
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static struct phy_ops rochchip_p3phy_ops = {
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.init = rochchip_p3phy_init,
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.exit = rochchip_p3phy_exit,
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.configure = rockchip_p3phy_configure,
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};
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static const struct udevice_id rockchip_p3phy_of_match[] = {
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{ .compatible = "rockchip,rk3568-pcie3-phy", .data = (ulong)&rk3568_ops},
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{ .compatible = "rockchip,rk3588-pcie3-phy", .data = (ulong)&rk3588_ops },
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{ },
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};
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U_BOOT_DRIVER(rockchip_pcie3phy) = {
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.name = "rockchip_pcie3phy",
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.id = UCLASS_PHY,
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.of_match = rockchip_p3phy_of_match,
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.ops = &rochchip_p3phy_ops,
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.probe = rockchip_p3phy_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_p3phy_priv),
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};
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