// SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*/
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/smp.h>
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#include <linux/ethtool.h>
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#include <linux/module.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/jiffies.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <asm/mipsregs.h>
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/*
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* fmn.h - For FMN credit configuration and registering fmn_handler.
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* FMN is communication mechanism that allows processing agents within
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* XLR/XLS to communicate each other.
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*/
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#include <asm/netlogic/xlr/fmn.h>
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#include "platform_net.h"
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#include "xlr_net.h"
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/*
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* The readl/writel implementation byteswaps on XLR/XLS, so
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* we need to use __raw_ IO to read the NAE registers
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* because they are in the big-endian MMIO area on the SoC.
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*/
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static inline void xlr_nae_wreg(u32 __iomem *base, unsigned int reg, u32 val)
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{
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__raw_writel(val, base + reg);
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}
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static inline u32 xlr_nae_rdreg(u32 __iomem *base, unsigned int reg)
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{
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return __raw_readl(base + reg);
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}
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static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask)
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{
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u32 tmp;
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tmp = xlr_nae_rdreg(base_addr, off);
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xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask));
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}
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#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
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static int send_to_rfr_fifo(struct xlr_net_priv *priv, void *addr)
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{
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struct nlm_fmn_msg msg;
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int ret = 0, num_try = 0, stnid;
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unsigned long paddr, mflags;
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paddr = virt_to_bus(addr);
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msg.msg0 = (u64)paddr & 0xffffffffe0ULL;
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msg.msg1 = 0;
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msg.msg2 = 0;
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msg.msg3 = 0;
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stnid = priv->nd->rfr_station;
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do {
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mflags = nlm_cop2_enable_irqsave();
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ret = nlm_fmn_send(1, 0, stnid, &msg);
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nlm_cop2_disable_irqrestore(mflags);
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if (ret == 0)
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return 0;
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} while (++num_try < 10000);
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netdev_err(priv->ndev, "Send to RFR failed in RX path\n");
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return ret;
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}
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static inline unsigned char *xlr_alloc_skb(void)
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{
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struct sk_buff *skb;
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int buf_len = sizeof(struct sk_buff *);
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unsigned char *skb_data;
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/* skb->data is cache aligned */
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skb = alloc_skb(XLR_RX_BUF_SIZE, GFP_ATOMIC);
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if (!skb)
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return NULL;
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skb_data = skb->data;
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skb_reserve(skb, MAC_SKB_BACK_PTR_SIZE);
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memcpy(skb_data, &skb, buf_len);
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return skb->data;
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}
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static void xlr_net_fmn_handler(int bkt, int src_stnid, int size, int code,
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struct nlm_fmn_msg *msg, void *arg)
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{
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struct sk_buff *skb;
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void *skb_data = NULL;
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struct net_device *ndev;
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struct xlr_net_priv *priv;
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u32 port, length;
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unsigned char *addr;
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struct xlr_adapter *adapter = arg;
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length = (msg->msg0 >> 40) & 0x3fff;
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if (length == 0) {
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addr = bus_to_virt(msg->msg0 & 0xffffffffffULL);
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addr = addr - MAC_SKB_BACK_PTR_SIZE;
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skb = (struct sk_buff *)(*(unsigned long *)addr);
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dev_kfree_skb_any((struct sk_buff *)addr);
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} else {
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addr = (unsigned char *)
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bus_to_virt(msg->msg0 & 0xffffffffe0ULL);
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length = length - BYTE_OFFSET - MAC_CRC_LEN;
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port = ((int)msg->msg0) & 0x0f;
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addr = addr - MAC_SKB_BACK_PTR_SIZE;
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skb = (struct sk_buff *)(*(unsigned long *)addr);
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skb->dev = adapter->netdev[port];
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if (!skb->dev)
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return;
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ndev = skb->dev;
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priv = netdev_priv(ndev);
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/* 16 byte IP header align */
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skb_reserve(skb, BYTE_OFFSET);
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skb_put(skb, length);
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skb->protocol = eth_type_trans(skb, skb->dev);
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netif_rx(skb);
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/* Fill rx ring */
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skb_data = xlr_alloc_skb();
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if (skb_data)
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send_to_rfr_fifo(priv, skb_data);
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}
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}
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static struct phy_device *xlr_get_phydev(struct xlr_net_priv *priv)
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{
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return mdiobus_get_phy(priv->mii_bus, priv->phy_addr);
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}
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/*
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* Ethtool operation
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*/
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static int xlr_get_link_ksettings(struct net_device *ndev,
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struct ethtool_link_ksettings *ecmd)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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struct phy_device *phydev = xlr_get_phydev(priv);
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if (!phydev)
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return -ENODEV;
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phy_ethtool_ksettings_get(phydev, ecmd);
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return 0;
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}
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static int xlr_set_link_ksettings(struct net_device *ndev,
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const struct ethtool_link_ksettings *ecmd)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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struct phy_device *phydev = xlr_get_phydev(priv);
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if (!phydev)
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return -ENODEV;
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return phy_ethtool_ksettings_set(phydev, ecmd);
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}
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static const struct ethtool_ops xlr_ethtool_ops = {
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.get_link_ksettings = xlr_get_link_ksettings,
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.set_link_ksettings = xlr_set_link_ksettings,
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};
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/*
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* Net operations
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*/
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static int xlr_net_fill_rx_ring(struct net_device *ndev)
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{
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void *skb_data;
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struct xlr_net_priv *priv = netdev_priv(ndev);
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int i;
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for (i = 0; i < MAX_FRIN_SPILL / 4; i++) {
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skb_data = xlr_alloc_skb();
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if (!skb_data)
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return -ENOMEM;
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send_to_rfr_fifo(priv, skb_data);
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}
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netdev_info(ndev, "Rx ring setup done\n");
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return 0;
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}
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static int xlr_net_open(struct net_device *ndev)
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{
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u32 err;
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struct xlr_net_priv *priv = netdev_priv(ndev);
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struct phy_device *phydev = xlr_get_phydev(priv);
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/* schedule a link state check */
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phy_start(phydev);
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err = phy_start_aneg(phydev);
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if (err) {
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pr_err("Autoneg failed\n");
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return err;
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}
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/* Setup the speed from PHY to internal reg*/
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xlr_set_gmac_speed(priv);
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netif_tx_start_all_queues(ndev);
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return 0;
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}
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static int xlr_net_stop(struct net_device *ndev)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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struct phy_device *phydev = xlr_get_phydev(priv);
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phy_stop(phydev);
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netif_tx_stop_all_queues(ndev);
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return 0;
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}
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static void xlr_make_tx_desc(struct nlm_fmn_msg *msg, unsigned long addr,
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struct sk_buff *skb)
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{
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unsigned long physkb = virt_to_phys(skb);
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int cpu_core = nlm_core_id();
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int fr_stn_id = cpu_core * 8 + XLR_FB_STN; /* FB to 6th bucket */
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msg->msg0 = (((u64)1 << 63) | /* End of packet descriptor */
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((u64)127 << 54) | /* No Free back */
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(u64)skb->len << 40 | /* Length of data */
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((u64)addr));
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msg->msg1 = (((u64)1 << 63) |
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((u64)fr_stn_id << 54) | /* Free back id */
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(u64)0 << 40 | /* Set len to 0 */
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((u64)physkb & 0xffffffff)); /* 32bit address */
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msg->msg2 = 0;
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msg->msg3 = 0;
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}
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static netdev_tx_t xlr_net_start_xmit(struct sk_buff *skb,
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struct net_device *ndev)
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{
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struct nlm_fmn_msg msg;
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struct xlr_net_priv *priv = netdev_priv(ndev);
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int ret;
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u32 flags;
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xlr_make_tx_desc(&msg, virt_to_phys(skb->data), skb);
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flags = nlm_cop2_enable_irqsave();
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ret = nlm_fmn_send(2, 0, priv->tx_stnid, &msg);
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nlm_cop2_disable_irqrestore(flags);
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if (ret)
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dev_kfree_skb_any(skb);
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return NETDEV_TX_OK;
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}
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static void xlr_hw_set_mac_addr(struct net_device *ndev)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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/* set mac station address */
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0,
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((ndev->dev_addr[5] << 24) | (ndev->dev_addr[4] << 16) |
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(ndev->dev_addr[3] << 8) | (ndev->dev_addr[2])));
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1,
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((ndev->dev_addr[1] << 24) | (ndev->dev_addr[0] << 16)));
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG,
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(1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID));
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if (priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII ||
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priv->nd->phy_interface == PHY_INTERFACE_MODE_SGMII)
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xlr_reg_update(priv->base_addr, R_IPG_IFG, MAC_B2B_IPG, 0x7f);
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}
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static int xlr_net_set_mac_addr(struct net_device *ndev, void *data)
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{
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int err;
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err = eth_mac_addr(ndev, data);
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if (err)
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return err;
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xlr_hw_set_mac_addr(ndev);
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return 0;
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}
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static void xlr_set_rx_mode(struct net_device *ndev)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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u32 regval;
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regval = xlr_nae_rdreg(priv->base_addr, R_MAC_FILTER_CONFIG);
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if (ndev->flags & IFF_PROMISC) {
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regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
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} else {
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regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
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}
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xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, regval);
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}
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static void xlr_stats(struct net_device *ndev, struct rtnl_link_stats64 *stats)
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{
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struct xlr_net_priv *priv = netdev_priv(ndev);
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stats->rx_packets = xlr_nae_rdreg(priv->base_addr, RX_PACKET_COUNTER);
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stats->tx_packets = xlr_nae_rdreg(priv->base_addr, TX_PACKET_COUNTER);
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stats->rx_bytes = xlr_nae_rdreg(priv->base_addr, RX_BYTE_COUNTER);
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stats->tx_bytes = xlr_nae_rdreg(priv->base_addr, TX_BYTE_COUNTER);
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stats->tx_errors = xlr_nae_rdreg(priv->base_addr, TX_FCS_ERROR_COUNTER);
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stats->rx_dropped = xlr_nae_rdreg(priv->base_addr,
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RX_DROP_PACKET_COUNTER);
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stats->tx_dropped = xlr_nae_rdreg(priv->base_addr,
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TX_DROP_FRAME_COUNTER);
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stats->multicast = xlr_nae_rdreg(priv->base_addr,
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RX_MULTICAST_PACKET_COUNTER);
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stats->collisions = xlr_nae_rdreg(priv->base_addr,
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TX_TOTAL_COLLISION_COUNTER);
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stats->rx_length_errors = xlr_nae_rdreg(priv->base_addr,
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RX_FRAME_LENGTH_ERROR_COUNTER);
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stats->rx_over_errors = xlr_nae_rdreg(priv->base_addr,
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RX_DROP_PACKET_COUNTER);
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stats->rx_crc_errors = xlr_nae_rdreg(priv->base_addr,
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RX_FCS_ERROR_COUNTER);
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stats->rx_frame_errors = xlr_nae_rdreg(priv->base_addr,
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RX_ALIGNMENT_ERROR_COUNTER);
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stats->rx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
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RX_DROP_PACKET_COUNTER);
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stats->rx_missed_errors = xlr_nae_rdreg(priv->base_addr,
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RX_CARRIER_SENSE_ERROR_COUNTER);
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stats->rx_errors = (stats->rx_over_errors + stats->rx_crc_errors +
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stats->rx_frame_errors + stats->rx_fifo_errors +
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stats->rx_missed_errors);
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stats->tx_aborted_errors = xlr_nae_rdreg(priv->base_addr,
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TX_EXCESSIVE_COLLISION_PACKET_COUNTER);
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stats->tx_carrier_errors = xlr_nae_rdreg(priv->base_addr,
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TX_DROP_FRAME_COUNTER);
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stats->tx_fifo_errors = xlr_nae_rdreg(priv->base_addr,
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TX_DROP_FRAME_COUNTER);
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}
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static const struct net_device_ops xlr_netdev_ops = {
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.ndo_open = xlr_net_open,
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.ndo_stop = xlr_net_stop,
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.ndo_start_xmit = xlr_net_start_xmit,
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.ndo_select_queue = dev_pick_tx_cpu_id,
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.ndo_set_mac_address = xlr_net_set_mac_addr,
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.ndo_set_rx_mode = xlr_set_rx_mode,
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.ndo_get_stats64 = xlr_stats,
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};
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/*
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* Gmac init
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*/
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static void *xlr_config_spill(struct xlr_net_priv *priv, int reg_start_0,
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int reg_start_1, int reg_size, int size)
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{
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void *spill;
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u32 *base;
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unsigned long phys_addr;
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u32 spill_size;
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base = priv->base_addr;
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spill_size = size;
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spill = kmalloc(spill_size + SMP_CACHE_BYTES, GFP_KERNEL);
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if (!spill)
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return ZERO_SIZE_PTR;
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spill = PTR_ALIGN(spill, SMP_CACHE_BYTES);
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phys_addr = virt_to_phys(spill);
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dev_dbg(&priv->ndev->dev, "Allocated spill %d bytes at %lx\n",
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size, phys_addr);
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xlr_nae_wreg(base, reg_start_0, (phys_addr >> 5) & 0xffffffff);
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xlr_nae_wreg(base, reg_start_1, ((u64)phys_addr >> 37) & 0x07);
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xlr_nae_wreg(base, reg_size, spill_size);
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return spill;
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}
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/*
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* Configure the 6 FIFO's that are used by the network accelarator to
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* communicate with the rest of the XLx device. 4 of the FIFO's are for
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* packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
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* the NA with free descriptors.
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*/
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static void xlr_config_fifo_spill_area(struct xlr_net_priv *priv)
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{
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priv->frin_spill = xlr_config_spill(priv,
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R_REG_FRIN_SPILL_MEM_START_0,
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R_REG_FRIN_SPILL_MEM_START_1,
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R_REG_FRIN_SPILL_MEM_SIZE,
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MAX_FRIN_SPILL * sizeof(u64));
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priv->frout_spill = xlr_config_spill(priv,
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R_FROUT_SPILL_MEM_START_0,
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R_FROUT_SPILL_MEM_START_1,
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R_FROUT_SPILL_MEM_SIZE,
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MAX_FROUT_SPILL * sizeof(u64));
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priv->class_0_spill = xlr_config_spill(priv,
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R_CLASS0_SPILL_MEM_START_0,
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R_CLASS0_SPILL_MEM_START_1,
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R_CLASS0_SPILL_MEM_SIZE,
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MAX_CLASS_0_SPILL * sizeof(u64));
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priv->class_1_spill = xlr_config_spill(priv,
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R_CLASS1_SPILL_MEM_START_0,
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R_CLASS1_SPILL_MEM_START_1,
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R_CLASS1_SPILL_MEM_SIZE,
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MAX_CLASS_1_SPILL * sizeof(u64));
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priv->class_2_spill = xlr_config_spill(priv,
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R_CLASS2_SPILL_MEM_START_0,
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R_CLASS2_SPILL_MEM_START_1,
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R_CLASS2_SPILL_MEM_SIZE,
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MAX_CLASS_2_SPILL * sizeof(u64));
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priv->class_3_spill = xlr_config_spill(priv,
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R_CLASS3_SPILL_MEM_START_0,
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R_CLASS3_SPILL_MEM_START_1,
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R_CLASS3_SPILL_MEM_SIZE,
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MAX_CLASS_3_SPILL * sizeof(u64));
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}
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/*
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* Configure PDE to Round-Robin distribution of packets to the
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* available cpu
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*/
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static void xlr_config_pde(struct xlr_net_priv *priv)
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{
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int i = 0;
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u64 bkt_map = 0;
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/* Each core has 8 buckets(station) */
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for (i = 0; i < hweight32(priv->nd->cpu_mask); i++)
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bkt_map |= (0xff << (i * 8));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0, (bkt_map & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_0 + 1,
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((bkt_map >> 32) & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1, (bkt_map & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_1 + 1,
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((bkt_map >> 32) & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2, (bkt_map & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_2 + 1,
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((bkt_map >> 32) & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3, (bkt_map & 0xffffffff));
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xlr_nae_wreg(priv->base_addr, R_PDE_CLASS_3 + 1,
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((bkt_map >> 32) & 0xffffffff));
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}
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/*
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* Setup the Message ring credits, bucket size and other
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* common configuration
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*/
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static int xlr_config_common(struct xlr_net_priv *priv)
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{
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struct xlr_fmn_info *gmac = priv->nd->gmac_fmn_info;
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int start_stn_id = gmac->start_stn_id;
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int end_stn_id = gmac->end_stn_id;
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int *bucket_size = priv->nd->bucket_size;
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int i, j, err;
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/* Setting non-core MsgBktSize(0x321 - 0x325) */
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for (i = start_stn_id; i <= end_stn_id; i++) {
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xlr_nae_wreg(priv->base_addr,
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R_GMAC_RFR0_BUCKET_SIZE + i - start_stn_id,
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bucket_size[i]);
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}
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/*
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* Setting non-core Credit counter register
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* Distributing Gmac's credit to CPU's
|
*/
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for (i = 0; i < 8; i++) {
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for (j = 0; j < 8; j++)
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xlr_nae_wreg(priv->base_addr,
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(R_CC_CPU0_0 + (i * 8)) + j,
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gmac->credit_config[(i * 8) + j]);
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}
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xlr_nae_wreg(priv->base_addr, R_MSG_TX_THRESHOLD, 3);
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xlr_nae_wreg(priv->base_addr, R_DMACR0, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_DMACR1, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_DMACR2, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_DMACR3, 0xffffffff);
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xlr_nae_wreg(priv->base_addr, R_FREEQCARVE, 0);
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err = xlr_net_fill_rx_ring(priv->ndev);
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if (err)
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return err;
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nlm_register_fmn_handler(start_stn_id, end_stn_id, xlr_net_fmn_handler,
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priv->adapter);
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return 0;
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}
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static void xlr_config_translate_table(struct xlr_net_priv *priv)
|
{
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u32 cpu_mask;
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u32 val;
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int bkts[32]; /* one bucket is assumed for each cpu */
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int b1, b2, c1, c2, i, j, k;
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int use_bkt;
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use_bkt = 0;
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cpu_mask = priv->nd->cpu_mask;
|
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pr_info("Using %s-based distribution\n",
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(use_bkt) ? "bucket" : "class");
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j = 0;
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for (i = 0; i < 32; i++) {
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if ((1 << i) & cpu_mask) {
|
/* for each cpu, mark the 4+threadid bucket */
|
bkts[j] = ((i / 4) * 8) + (i % 4);
|
j++;
|
}
|
}
|
|
/*configure the 128 * 9 Translation table to send to available buckets*/
|
k = 0;
|
c1 = 3;
|
c2 = 0;
|
for (i = 0; i < 64; i++) {
|
/*
|
* On use_bkt set the b0, b1 are used, else
|
* the 4 classes are used, here implemented
|
* a logic to distribute the packets to the
|
* buckets equally or based on the class
|
*/
|
c1 = (c1 + 1) & 3;
|
c2 = (c1 + 1) & 3;
|
b1 = bkts[k];
|
k = (k + 1) % j;
|
b2 = bkts[k];
|
k = (k + 1) % j;
|
|
val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
|
(c2 << 7) | (b2 << 1) | (use_bkt << 0));
|
dev_dbg(&priv->ndev->dev, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
|
i, b1, b2, c1, c2);
|
xlr_nae_wreg(priv->base_addr, R_TRANSLATETABLE + i, val);
|
c1 = c2;
|
}
|
}
|
|
static void xlr_config_parser(struct xlr_net_priv *priv)
|
{
|
u32 val;
|
|
/* Mark it as ETHERNET type */
|
xlr_nae_wreg(priv->base_addr, R_L2TYPE_0, 0x01);
|
|
/* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
|
xlr_nae_wreg(priv->base_addr, R_PARSERCONFIGREG,
|
((0x7f << 8) | (1 << 1)));
|
|
/* configure the parser : L2 Type is configured in the bootloader */
|
/* extract IP: src, dest protocol */
|
xlr_nae_wreg(priv->base_addr, R_L3CTABLE,
|
(9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
|
(0x0800 << 0));
|
xlr_nae_wreg(priv->base_addr, R_L3CTABLE + 1,
|
(9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
|
(16 << 4) | 4);
|
|
/* Configure to extract SRC port and Dest port for TCP and UDP pkts */
|
xlr_nae_wreg(priv->base_addr, R_L4CTABLE, 6);
|
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 2, 17);
|
val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
|
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 1, val);
|
xlr_nae_wreg(priv->base_addr, R_L4CTABLE + 3, val);
|
|
xlr_config_translate_table(priv);
|
}
|
|
static int xlr_phy_write(u32 *base_addr, int phy_addr, int regnum, u16 val)
|
{
|
unsigned long timeout, stoptime, checktime;
|
int timedout;
|
|
/* 100ms timeout*/
|
timeout = msecs_to_jiffies(100);
|
stoptime = jiffies + timeout;
|
timedout = 0;
|
|
xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS, (phy_addr << 8) | regnum);
|
|
/* Write the data which starts the write cycle */
|
xlr_nae_wreg(base_addr, R_MII_MGMT_WRITE_DATA, (u32)val);
|
|
/* poll for the read cycle to complete */
|
while (!timedout) {
|
checktime = jiffies;
|
if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
|
break;
|
timedout = time_after(checktime, stoptime);
|
}
|
if (timedout) {
|
pr_info("Phy device write err: device busy");
|
return -EBUSY;
|
}
|
|
return 0;
|
}
|
|
static int xlr_phy_read(u32 *base_addr, int phy_addr, int regnum)
|
{
|
unsigned long timeout, stoptime, checktime;
|
int timedout;
|
|
/* 100ms timeout*/
|
timeout = msecs_to_jiffies(100);
|
stoptime = jiffies + timeout;
|
timedout = 0;
|
|
/* setup the phy reg to be used */
|
xlr_nae_wreg(base_addr, R_MII_MGMT_ADDRESS,
|
(phy_addr << 8) | (regnum << 0));
|
|
/* Issue the read command */
|
xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND,
|
(1 << O_MII_MGMT_COMMAND__rstat));
|
|
/* poll for the read cycle to complete */
|
while (!timedout) {
|
checktime = jiffies;
|
if (xlr_nae_rdreg(base_addr, R_MII_MGMT_INDICATORS) == 0)
|
break;
|
timedout = time_after(checktime, stoptime);
|
}
|
if (timedout) {
|
pr_info("Phy device read err: device busy");
|
return -EBUSY;
|
}
|
|
/* clear the read cycle */
|
xlr_nae_wreg(base_addr, R_MII_MGMT_COMMAND, 0);
|
|
/* Read the data */
|
return xlr_nae_rdreg(base_addr, R_MII_MGMT_STATUS);
|
}
|
|
static int xlr_mii_write(struct mii_bus *bus, int phy_addr, int regnum, u16 val)
|
{
|
struct xlr_net_priv *priv = bus->priv;
|
int ret;
|
|
ret = xlr_phy_write(priv->mii_addr, phy_addr, regnum, val);
|
dev_dbg(&priv->ndev->dev, "mii_write phy %d : %d <- %x [%x]\n",
|
phy_addr, regnum, val, ret);
|
return ret;
|
}
|
|
static int xlr_mii_read(struct mii_bus *bus, int phy_addr, int regnum)
|
{
|
struct xlr_net_priv *priv = bus->priv;
|
int ret;
|
|
ret = xlr_phy_read(priv->mii_addr, phy_addr, regnum);
|
dev_dbg(&priv->ndev->dev, "mii_read phy %d : %d [%x]\n",
|
phy_addr, regnum, ret);
|
return ret;
|
}
|
|
/*
|
* XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
|
* which can be configured either SGMII or RGMII, considered SGMII
|
* by default, if board setup to RGMII the port_type need to set
|
* accordingly.Serdes and PCS layer need to configured for SGMII
|
*/
|
static void xlr_sgmii_init(struct xlr_net_priv *priv)
|
{
|
int phy;
|
|
xlr_phy_write(priv->serdes_addr, 26, 0, 0x6DB0);
|
xlr_phy_write(priv->serdes_addr, 26, 1, 0xFFFF);
|
xlr_phy_write(priv->serdes_addr, 26, 2, 0xB6D0);
|
xlr_phy_write(priv->serdes_addr, 26, 3, 0x00FF);
|
xlr_phy_write(priv->serdes_addr, 26, 4, 0x0000);
|
xlr_phy_write(priv->serdes_addr, 26, 5, 0x0000);
|
xlr_phy_write(priv->serdes_addr, 26, 6, 0x0005);
|
xlr_phy_write(priv->serdes_addr, 26, 7, 0x0001);
|
xlr_phy_write(priv->serdes_addr, 26, 8, 0x0000);
|
xlr_phy_write(priv->serdes_addr, 26, 9, 0x0000);
|
xlr_phy_write(priv->serdes_addr, 26, 10, 0x0000);
|
|
/* program GPIO values for serdes init parameters */
|
xlr_nae_wreg(priv->gpio_addr, 0x20, 0x7e6802);
|
xlr_nae_wreg(priv->gpio_addr, 0x10, 0x7104);
|
|
xlr_nae_wreg(priv->gpio_addr, 0x22, 0x7e6802);
|
xlr_nae_wreg(priv->gpio_addr, 0x21, 0x7104);
|
|
/* enable autoneg - more magic */
|
phy = priv->phy_addr % 4 + 27;
|
xlr_phy_write(priv->pcs_addr, phy, 0, 0x1000);
|
xlr_phy_write(priv->pcs_addr, phy, 0, 0x0200);
|
}
|
|
void xlr_set_gmac_speed(struct xlr_net_priv *priv)
|
{
|
struct phy_device *phydev = xlr_get_phydev(priv);
|
int speed;
|
|
if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
|
xlr_sgmii_init(priv);
|
|
if (phydev->speed != priv->phy_speed) {
|
speed = phydev->speed;
|
if (speed == SPEED_1000) {
|
/* Set interface to Byte mode */
|
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
|
priv->phy_speed = speed;
|
} else if (speed == SPEED_100 || speed == SPEED_10) {
|
/* Set interface to Nibble mode */
|
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7117);
|
priv->phy_speed = speed;
|
}
|
/* Set SGMII speed in Interface control reg */
|
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
|
if (speed == SPEED_10)
|
xlr_nae_wreg(priv->base_addr,
|
R_INTERFACE_CONTROL,
|
SGMII_SPEED_10);
|
if (speed == SPEED_100)
|
xlr_nae_wreg(priv->base_addr,
|
R_INTERFACE_CONTROL,
|
SGMII_SPEED_100);
|
if (speed == SPEED_1000)
|
xlr_nae_wreg(priv->base_addr,
|
R_INTERFACE_CONTROL,
|
SGMII_SPEED_1000);
|
}
|
if (speed == SPEED_10)
|
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x2);
|
if (speed == SPEED_100)
|
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x1);
|
if (speed == SPEED_1000)
|
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x0);
|
}
|
pr_info("gmac%d : %dMbps\n", priv->port_id, priv->phy_speed);
|
}
|
|
static void xlr_gmac_link_adjust(struct net_device *ndev)
|
{
|
struct xlr_net_priv *priv = netdev_priv(ndev);
|
struct phy_device *phydev = xlr_get_phydev(priv);
|
u32 intreg;
|
|
intreg = xlr_nae_rdreg(priv->base_addr, R_INTREG);
|
if (phydev->link) {
|
if (phydev->speed != priv->phy_speed) {
|
xlr_set_gmac_speed(priv);
|
pr_info("gmac%d : Link up\n", priv->port_id);
|
}
|
} else {
|
xlr_set_gmac_speed(priv);
|
pr_info("gmac%d : Link down\n", priv->port_id);
|
}
|
}
|
|
static int xlr_mii_probe(struct xlr_net_priv *priv)
|
{
|
struct phy_device *phydev = xlr_get_phydev(priv);
|
|
if (!phydev) {
|
pr_err("no PHY found on phy_addr %d\n", priv->phy_addr);
|
return -ENODEV;
|
}
|
|
/* Attach MAC to PHY */
|
phydev = phy_connect(priv->ndev, phydev_name(phydev),
|
xlr_gmac_link_adjust, priv->nd->phy_interface);
|
|
if (IS_ERR(phydev)) {
|
pr_err("could not attach PHY\n");
|
return PTR_ERR(phydev);
|
}
|
phydev->supported &= (ADVERTISED_10baseT_Full
|
| ADVERTISED_10baseT_Half
|
| ADVERTISED_100baseT_Full
|
| ADVERTISED_100baseT_Half
|
| ADVERTISED_1000baseT_Full
|
| ADVERTISED_Autoneg
|
| ADVERTISED_MII);
|
|
phydev->advertising = phydev->supported;
|
phy_attached_info(phydev);
|
return 0;
|
}
|
|
static int xlr_setup_mdio(struct xlr_net_priv *priv,
|
struct platform_device *pdev)
|
{
|
int err;
|
|
priv->mii_bus = mdiobus_alloc();
|
if (!priv->mii_bus) {
|
pr_err("mdiobus alloc failed\n");
|
return -ENOMEM;
|
}
|
|
priv->mii_bus->priv = priv;
|
priv->mii_bus->name = "xlr-mdio";
|
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
|
priv->mii_bus->name, priv->port_id);
|
priv->mii_bus->read = xlr_mii_read;
|
priv->mii_bus->write = xlr_mii_write;
|
priv->mii_bus->parent = &pdev->dev;
|
|
/* Scan only the enabled address */
|
priv->mii_bus->phy_mask = ~(1 << priv->phy_addr);
|
|
/* setting clock divisor to 54 */
|
xlr_nae_wreg(priv->base_addr, R_MII_MGMT_CONFIG, 0x7);
|
|
err = mdiobus_register(priv->mii_bus);
|
if (err) {
|
mdiobus_free(priv->mii_bus);
|
pr_err("mdio bus registration failed\n");
|
return err;
|
}
|
|
pr_info("Registered mdio bus id : %s\n", priv->mii_bus->id);
|
err = xlr_mii_probe(priv);
|
if (err) {
|
mdiobus_free(priv->mii_bus);
|
return err;
|
}
|
return 0;
|
}
|
|
static void xlr_port_enable(struct xlr_net_priv *priv)
|
{
|
u32 prid = (read_c0_prid() & 0xf000);
|
|
/* Setup MAC_CONFIG reg if (xls & rgmii) */
|
if ((prid == 0x8000 || prid == 0x4000 || prid == 0xc000) &&
|
priv->nd->phy_interface == PHY_INTERFACE_MODE_RGMII)
|
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
|
(1 << O_RX_CONTROL__RGMII),
|
(1 << O_RX_CONTROL__RGMII));
|
|
/* Rx Tx enable */
|
xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
|
((1 << O_MAC_CONFIG_1__rxen) |
|
(1 << O_MAC_CONFIG_1__txen) |
|
(1 << O_MAC_CONFIG_1__rxfc) |
|
(1 << O_MAC_CONFIG_1__txfc)),
|
((1 << O_MAC_CONFIG_1__rxen) |
|
(1 << O_MAC_CONFIG_1__txen) |
|
(1 << O_MAC_CONFIG_1__rxfc) |
|
(1 << O_MAC_CONFIG_1__txfc)));
|
|
/* Setup tx control reg */
|
xlr_reg_update(priv->base_addr, R_TX_CONTROL,
|
((1 << O_TX_CONTROL__TXENABLE) |
|
(512 << O_TX_CONTROL__TXTHRESHOLD)), 0x3fff);
|
|
/* Setup rx control reg */
|
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
|
1 << O_RX_CONTROL__RXENABLE,
|
1 << O_RX_CONTROL__RXENABLE);
|
}
|
|
static void xlr_port_disable(struct xlr_net_priv *priv)
|
{
|
/* Setup MAC_CONFIG reg */
|
/* Rx Tx disable*/
|
xlr_reg_update(priv->base_addr, R_MAC_CONFIG_1,
|
((1 << O_MAC_CONFIG_1__rxen) |
|
(1 << O_MAC_CONFIG_1__txen) |
|
(1 << O_MAC_CONFIG_1__rxfc) |
|
(1 << O_MAC_CONFIG_1__txfc)), 0x0);
|
|
/* Setup tx control reg */
|
xlr_reg_update(priv->base_addr, R_TX_CONTROL,
|
((1 << O_TX_CONTROL__TXENABLE) |
|
(512 << O_TX_CONTROL__TXTHRESHOLD)), 0);
|
|
/* Setup rx control reg */
|
xlr_reg_update(priv->base_addr, R_RX_CONTROL,
|
1 << O_RX_CONTROL__RXENABLE, 0);
|
}
|
|
/*
|
* Initialization of gmac
|
*/
|
static int xlr_gmac_init(struct xlr_net_priv *priv,
|
struct platform_device *pdev)
|
{
|
int ret;
|
|
pr_info("Initializing the gmac%d\n", priv->port_id);
|
|
xlr_port_disable(priv);
|
|
xlr_nae_wreg(priv->base_addr, R_DESC_PACK_CTRL,
|
(1 << O_DESC_PACK_CTRL__MAXENTRY) |
|
(BYTE_OFFSET << O_DESC_PACK_CTRL__BYTEOFFSET) |
|
(1600 << O_DESC_PACK_CTRL__REGULARSIZE));
|
|
ret = xlr_setup_mdio(priv, pdev);
|
if (ret)
|
return ret;
|
xlr_port_enable(priv);
|
|
/* Enable Full-duplex/1000Mbps/CRC */
|
xlr_nae_wreg(priv->base_addr, R_MAC_CONFIG_2, 0x7217);
|
/* speed 2.5Mhz */
|
xlr_nae_wreg(priv->base_addr, R_CORECONTROL, 0x02);
|
/* Setup Interrupt mask reg */
|
xlr_nae_wreg(priv->base_addr, R_INTMASK, (1 << O_INTMASK__TXILLEGAL) |
|
(1 << O_INTMASK__MDINT) | (1 << O_INTMASK__TXFETCHERROR) |
|
(1 << O_INTMASK__P2PSPILLECC) | (1 << O_INTMASK__TAGFULL) |
|
(1 << O_INTMASK__UNDERRUN) | (1 << O_INTMASK__ABORT));
|
|
/* Clear all stats */
|
xlr_reg_update(priv->base_addr, R_STATCTRL, 0, 1 << O_STATCTRL__CLRCNT);
|
xlr_reg_update(priv->base_addr, R_STATCTRL, 1 << 2, 1 << 2);
|
return 0;
|
}
|
|
static int xlr_net_probe(struct platform_device *pdev)
|
{
|
struct xlr_net_priv *priv = NULL;
|
struct net_device *ndev;
|
struct resource *res;
|
struct xlr_adapter *adapter;
|
int err, port;
|
|
pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev->id);
|
/*
|
* Allocate our adapter data structure and attach it to the device.
|
*/
|
adapter = devm_kzalloc(&pdev->dev, sizeof(*adapter), GFP_KERNEL);
|
if (!adapter)
|
return -ENOMEM;
|
|
/*
|
* XLR and XLS have 1 and 2 NAE controller respectively
|
* Each controller has 4 gmac ports, mapping each controller
|
* under one parent device, 4 gmac ports under one device.
|
*/
|
for (port = 0; port < pdev->num_resources / 2; port++) {
|
ndev = alloc_etherdev_mq(sizeof(struct xlr_net_priv), 32);
|
if (!ndev) {
|
dev_err(&pdev->dev,
|
"Allocation of Ethernet device failed\n");
|
return -ENOMEM;
|
}
|
|
priv = netdev_priv(ndev);
|
priv->pdev = pdev;
|
priv->ndev = ndev;
|
priv->port_id = (pdev->id * 4) + port;
|
priv->nd = (struct xlr_net_data *)pdev->dev.platform_data;
|
priv->base_addr = devm_platform_ioremap_resource(pdev, port);
|
if (IS_ERR(priv->base_addr)) {
|
err = PTR_ERR(priv->base_addr);
|
goto err_gmac;
|
}
|
priv->adapter = adapter;
|
adapter->netdev[port] = ndev;
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, port);
|
if (!res) {
|
dev_err(&pdev->dev, "No irq resource for MAC %d\n",
|
priv->port_id);
|
err = -ENODEV;
|
goto err_gmac;
|
}
|
|
ndev->irq = res->start;
|
|
priv->phy_addr = priv->nd->phy_addr[port];
|
priv->tx_stnid = priv->nd->tx_stnid[port];
|
priv->mii_addr = priv->nd->mii_addr;
|
priv->serdes_addr = priv->nd->serdes_addr;
|
priv->pcs_addr = priv->nd->pcs_addr;
|
priv->gpio_addr = priv->nd->gpio_addr;
|
|
ndev->netdev_ops = &xlr_netdev_ops;
|
ndev->watchdog_timeo = HZ;
|
|
/* Setup Mac address and Rx mode */
|
eth_hw_addr_random(ndev);
|
xlr_hw_set_mac_addr(ndev);
|
xlr_set_rx_mode(ndev);
|
|
priv->num_rx_desc += MAX_NUM_DESC_SPILL;
|
ndev->ethtool_ops = &xlr_ethtool_ops;
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
xlr_config_fifo_spill_area(priv);
|
/* Configure PDE to Round-Robin pkt distribution */
|
xlr_config_pde(priv);
|
xlr_config_parser(priv);
|
|
/* Call init with respect to port */
|
if (strcmp(res->name, "gmac") == 0) {
|
err = xlr_gmac_init(priv, pdev);
|
if (err) {
|
dev_err(&pdev->dev, "gmac%d init failed\n",
|
priv->port_id);
|
goto err_gmac;
|
}
|
}
|
|
if (priv->port_id == 0 || priv->port_id == 4) {
|
err = xlr_config_common(priv);
|
if (err)
|
goto err_netdev;
|
}
|
|
err = register_netdev(ndev);
|
if (err) {
|
dev_err(&pdev->dev,
|
"Registering netdev failed for gmac%d\n",
|
priv->port_id);
|
goto err_netdev;
|
}
|
platform_set_drvdata(pdev, priv);
|
}
|
|
return 0;
|
|
err_netdev:
|
mdiobus_free(priv->mii_bus);
|
err_gmac:
|
free_netdev(ndev);
|
return err;
|
}
|
|
static int xlr_net_remove(struct platform_device *pdev)
|
{
|
struct xlr_net_priv *priv = platform_get_drvdata(pdev);
|
|
unregister_netdev(priv->ndev);
|
mdiobus_unregister(priv->mii_bus);
|
mdiobus_free(priv->mii_bus);
|
free_netdev(priv->ndev);
|
return 0;
|
}
|
|
static struct platform_driver xlr_net_driver = {
|
.probe = xlr_net_probe,
|
.remove = xlr_net_remove,
|
.driver = {
|
.name = "xlr-net",
|
},
|
};
|
|
module_platform_driver(xlr_net_driver);
|
|
MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
|
MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
|
MODULE_LICENSE("Dual BSD/GPL");
|
MODULE_ALIAS("platform:xlr-net");
|
