/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 Sanechips Technology Co., Ltd.
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* Copyright 2017 Linaro Ltd.
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*/
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#ifndef __PINCTRL_ZX_H
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#define __PINCTRL_ZX_H
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/**
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* struct zx_mux_desc - hardware mux descriptor
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* @name: mux function name
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* @muxval: mux register bit value
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*/
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struct zx_mux_desc {
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const char *name;
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u8 muxval;
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};
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/**
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* struct zx_pin_data - hardware per-pin data
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* @aon_pin: whether it's an AON pin
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* @offset: register offset within TOP pinmux controller
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* @bitpos: bit position within TOP pinmux register
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* @width: bit width within TOP pinmux register
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* @coffset: pinconf register offset within AON controller
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* @cbitpos: pinconf bit position within AON register
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* @muxes: available mux function names and corresponding register values
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*
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* Unlike TOP pinmux and AON pinconf registers which are arranged pretty
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* arbitrarily, AON pinmux register bits are well organized per pin id, and
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* each pin occupies two bits, so that we can calculate the AON register offset
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* and bit position from pin id. Thus, we only need to define TOP pinmux and
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* AON pinconf register data for the pin.
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*/
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struct zx_pin_data {
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bool aon_pin;
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u16 offset;
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u16 bitpos;
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u16 width;
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u16 coffset;
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u16 cbitpos;
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struct zx_mux_desc *muxes;
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};
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struct zx_pinctrl_soc_info {
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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};
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#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \
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.number = pin, \
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.name = #pin, \
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.drv_data = &(struct zx_pin_data) { \
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.aon_pin = false, \
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.offset = off, \
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.bitpos = bp, \
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.width = wd, \
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.coffset = coff, \
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.cbitpos = cbp, \
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.muxes = (struct zx_mux_desc[]) { \
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__VA_ARGS__, { } }, \
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}, \
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}
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#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \
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.number = pin, \
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.name = #pin, \
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.drv_data = &(struct zx_pin_data) { \
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.aon_pin = true, \
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.offset = off, \
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.bitpos = bp, \
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.width = wd, \
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.coffset = coff, \
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.cbitpos = cbp, \
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.muxes = (struct zx_mux_desc[]) { \
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__VA_ARGS__, { } }, \
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}, \
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}
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#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin)
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#define TOP_MUX(_val, _name) { \
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.name = _name, \
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.muxval = _val, \
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}
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/*
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* When the flag is set, it's a mux configuration for an AON pin that sits in
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* AON register. Otherwise, it's one for AON pin but sitting in TOP register.
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*/
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#define AON_MUX_FLAG BIT(7)
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#define AON_MUX(_val, _name) { \
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.name = _name, \
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.muxval = _val | AON_MUX_FLAG, \
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}
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int zx_pinctrl_init(struct platform_device *pdev,
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struct zx_pinctrl_soc_info *info);
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#endif /* __PINCTRL_ZX_H */
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