/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2015 - 2020 Intel Corporation */
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#ifndef ADF_C3XXXVF_HW_DATA_H_
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#define ADF_C3XXXVF_HW_DATA_H_
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#define ADF_C3XXXIOV_PMISC_BAR 1
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#define ADF_C3XXXIOV_ACCELERATORS_MASK 0x1
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#define ADF_C3XXXIOV_ACCELENGINES_MASK 0x1
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#define ADF_C3XXXIOV_MAX_ACCELERATORS 1
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#define ADF_C3XXXIOV_MAX_ACCELENGINES 1
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#define ADF_C3XXXIOV_RX_RINGS_OFFSET 8
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#define ADF_C3XXXIOV_TX_RINGS_MASK 0xFF
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#define ADF_C3XXXIOV_ETR_BAR 0
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#define ADF_C3XXXIOV_ETR_MAX_BANKS 1
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#define ADF_C3XXXIOV_PF2VF_OFFSET 0x200
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#define ADF_C3XXXIOV_VINTMSK_OFFSET 0x208
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void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data);
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void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data);
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#endif
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