/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Cavium, Inc.
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*/
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#ifndef __CPTVF_H
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#define __CPTVF_H
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#include <linux/list.h>
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#include "cpt_common.h"
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/* Default command queue length */
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#define CPT_CMD_QLEN 2046
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#define CPT_CMD_QCHUNK_SIZE 1023
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/* Default command timeout in seconds */
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#define CPT_COMMAND_TIMEOUT 4
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#define CPT_TIMER_THOLD 0xFFFF
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#define CPT_NUM_QS_PER_VF 1
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#define CPT_INST_SIZE 64
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#define CPT_NEXT_CHUNK_PTR_SIZE 8
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#define CPT_VF_MSIX_VECTORS 2
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#define CPT_VF_INTR_MBOX_MASK BIT(0)
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#define CPT_VF_INTR_DOVF_MASK BIT(1)
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#define CPT_VF_INTR_IRDE_MASK BIT(2)
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#define CPT_VF_INTR_NWRP_MASK BIT(3)
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#define CPT_VF_INTR_SERR_MASK BIT(4)
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#define DMA_DIRECT_DIRECT 0 /* Input DIRECT, Output DIRECT */
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#define DMA_GATHER_SCATTER 1
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#define FROM_DPTR 1
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/**
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* Enumeration cpt_vf_int_vec_e
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*
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* CPT VF MSI-X Vector Enumeration
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* Enumerates the MSI-X interrupt vectors.
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*/
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enum cpt_vf_int_vec_e {
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CPT_VF_INT_VEC_E_MISC = 0x00,
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CPT_VF_INT_VEC_E_DONE = 0x01
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};
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struct command_chunk {
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u8 *head;
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dma_addr_t dma_addr;
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u32 size; /* Chunk size, max CPT_INST_CHUNK_MAX_SIZE */
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struct hlist_node nextchunk;
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};
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struct command_queue {
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spinlock_t lock; /* command queue lock */
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u32 idx; /* Command queue host write idx */
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u32 nchunks; /* Number of command chunks */
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struct command_chunk *qhead; /* Command queue head, instructions
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* are inserted here
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*/
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struct hlist_head chead;
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};
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struct command_qinfo {
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u32 cmd_size;
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u32 qchunksize; /* Command queue chunk size */
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struct command_queue queue[CPT_NUM_QS_PER_VF];
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};
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struct pending_entry {
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u8 busy; /* Entry status (free/busy) */
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volatile u64 *completion_addr; /* Completion address */
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void *post_arg;
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void (*callback)(int, void *); /* Kernel ASYNC request callabck */
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void *callback_arg; /* Kernel ASYNC request callabck arg */
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};
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struct pending_queue {
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struct pending_entry *head; /* head of the queue */
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u32 front; /* Process work from here */
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u32 rear; /* Append new work here */
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atomic64_t pending_count;
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spinlock_t lock; /* Queue lock */
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};
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struct pending_qinfo {
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u32 nr_queues; /* Number of queues supported */
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u32 qlen; /* Queue length */
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struct pending_queue queue[CPT_NUM_QS_PER_VF];
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};
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#define for_each_pending_queue(qinfo, q, i) \
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for (i = 0, q = &qinfo->queue[i]; i < qinfo->nr_queues; i++, \
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q = &qinfo->queue[i])
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struct cpt_vf {
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u16 flags; /* Flags to hold device status bits */
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u8 vfid; /* Device Index 0...CPT_MAX_VF_NUM */
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u8 vftype; /* VF type of SE_TYPE(1) or AE_TYPE(1) */
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u8 vfgrp; /* VF group (0 - 8) */
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u8 node; /* Operating node: Bits (46:44) in BAR0 address */
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u8 priority; /* VF priority ring: 1-High proirity round
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* robin ring;0-Low priority round robin ring;
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*/
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struct pci_dev *pdev; /* pci device handle */
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void __iomem *reg_base; /* Register start address */
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void *wqe_info; /* BH worker info */
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/* MSI-X */
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cpumask_var_t affinity_mask[CPT_VF_MSIX_VECTORS];
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/* Command and Pending queues */
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u32 qsize;
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u32 nr_queues;
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struct command_qinfo cqinfo; /* Command queue information */
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struct pending_qinfo pqinfo; /* Pending queue information */
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/* VF-PF mailbox communication */
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bool pf_acked;
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bool pf_nacked;
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};
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int cptvf_send_vf_up(struct cpt_vf *cptvf);
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int cptvf_send_vf_down(struct cpt_vf *cptvf);
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int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf);
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int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf);
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int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
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int cptvf_check_pf_ready(struct cpt_vf *cptvf);
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void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
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void cvm_crypto_exit(void);
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int cvm_crypto_init(struct cpt_vf *cptvf);
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void vq_post_process(struct cpt_vf *cptvf, u32 qno);
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void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val);
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#endif /* __CPTVF_H */
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