/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 Cavium, Inc.
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*/
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#ifndef __CPTPF_H
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#define __CPTPF_H
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#include "cpt_common.h"
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#define CSR_DELAY 30
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#define CPT_MAX_CORE_GROUPS 8
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#define CPT_MAX_SE_CORES 10
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#define CPT_MAX_AE_CORES 6
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#define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
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#define CPT_MAX_VF_NUM 16
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#define CPT_PF_MSIX_VECTORS 3
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#define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
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#define CPT_UCODE_VERSION_SZ 32
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struct cpt_device;
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struct microcode {
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u8 is_mc_valid;
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u8 is_ae;
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u8 group;
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u8 num_cores;
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u32 code_size;
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u64 core_mask;
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u8 version[CPT_UCODE_VERSION_SZ];
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/* Base info */
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dma_addr_t phys_base;
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void *code;
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};
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struct cpt_vf_info {
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u8 state;
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u8 priority;
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u8 id;
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u32 qlen;
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};
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/**
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* cpt device structure
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*/
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struct cpt_device {
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u16 flags; /* Flags to hold device status bits */
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u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
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struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
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void __iomem *reg_base; /* Register start address */
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struct pci_dev *pdev; /* pci device handle */
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struct microcode mcode[CPT_MAX_CORE_GROUPS];
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u8 next_mc_idx; /* next microcode index */
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u8 next_group;
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u8 max_se_cores;
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u8 max_ae_cores;
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};
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void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
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#endif /* __CPTPF_H */
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