// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3588.dtsi"
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#include "rk3588-evb.dtsi"
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#include "rk3588-rk806-dual.dtsi"
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/ {
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dsm_sound: dsm-sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,name = "rockchip,dsm-sound";
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simple-audio-card,bitclock-master = <&sndcodec>;
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simple-audio-card,frame-master = <&sndcodec>;
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sndcpu: simple-audio-card,cpu {
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sound-dai = <&i2s3_2ch>;
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};
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sndcodec: simple-audio-card,codec {
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sound-dai = <&acdcdig_dsm>;
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};
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};
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fan: pwm-fan {
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compatible = "pwm-fan";
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#cooling-cells = <2>;
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pwms = <&pwm9 0 50000 0>;
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cooling-levels = <0 50 100 150 200 255>;
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rockchip,temp-trips = <
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50000 1
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55000 2
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60000 3
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65000 4
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70000 5
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>;
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};
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hdmiin_dc: hdmiin-dc {
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compatible = "rockchip,dummy-codec";
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#sound-dai-cells = <0>;
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};
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hdmiin-sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "i2s";
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simple-audio-card,name = "rockchip,hdmiin";
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simple-audio-card,bitclock-master = <&dailink0_master>;
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simple-audio-card,frame-master = <&dailink0_master>;
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status = "okay";
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simple-audio-card,cpu {
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sound-dai = <&i2s7_8ch>;
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};
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dailink0_master: simple-audio-card,codec {
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sound-dai = <&hdmiin_dc>;
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};
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};
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pcie20_avdd0v85: pcie20-avdd0v85 {
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compatible = "regulator-fixed";
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regulator-name = "pcie20_avdd0v85";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <850000>;
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vin-supply = <&avdd_0v85_s0>;
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};
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pcie20_avdd1v8: pcie20-avdd1v8 {
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compatible = "regulator-fixed";
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regulator-name = "pcie20_avdd1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&avcc_1v8_s0>;
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};
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pcie30_avdd0v75: pcie30-avdd0v75 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd0v75";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <750000>;
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vin-supply = <&avdd_0v75_s0>;
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};
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pcie30_avdd1v8: pcie30-avdd1v8 {
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compatible = "regulator-fixed";
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regulator-name = "pcie30_avdd1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&avcc_1v8_s0>;
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};
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vcc3v3_pcie30: vcc3v3-pcie30 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie30";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <5000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&acdcdig_dsm {
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status = "okay";
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};
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&combphy0_ps {
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status = "okay";
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};
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&combphy1_ps {
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status = "okay";
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};
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&combphy2_psu {
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status = "okay";
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};
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/*
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* mipi_dcphy0 needs to be enabled
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* when dsi0 is enabled
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*/
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&dsi0 {
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status = "disabled";
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};
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&dsi0_in_vp2 {
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status = "disabled";
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};
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&dsi0_in_vp3 {
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status = "okay";
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};
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/*
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* mipi_dcphy1 needs to be enabled
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* when dsi1 is enabled
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*/
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&dsi1 {
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status = "disabled";
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};
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&dsi1_in_vp2 {
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status = "disabled";
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};
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&dsi1_in_vp3 {
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status = "disabled";
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};
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&hdmi1 {
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enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&hdmi1_in_vp0 {
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status = "okay";
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};
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&hdmi1_sound {
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status = "okay";
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};
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&hdptxphy_hdmi1 {
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status = "okay";
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};
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&i2s3_2ch {
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status = "okay";
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/delete-property/ pinctrl-names;
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/delete-property/ pinctrl-0;
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};
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&i2s6_8ch {
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status = "okay";
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};
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&i2s7_8ch {
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status = "okay";
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};
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&mipi_dcphy0 {
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status = "disabled";
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};
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&mipi_dcphy1 {
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status = "disabled";
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};
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&pcie2x1l0 {
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reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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&pcie2x1l1 {
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reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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&pcie2x1l2 {
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reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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&pcie30phy {
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rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>;
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status = "okay";
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};
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&pcie3x2 {
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reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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&pcie3x4 {
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num-lanes = <2>;
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reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie30x4_clkreqn_m1>;
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status = "okay";
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};
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&pinctrl {
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pcie30x4 {
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pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
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rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&pwm9 {
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pinctrl-0 = <&pwm9m2_pins>;
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status = "okay";
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};
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&route_dsi0 {
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status = "okay";
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connect = <&vp3_out_dsi0>;
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};
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&route_dsi1 {
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status = "disabled";
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connect = <&vp3_out_dsi1>;
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};
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&spdif_tx1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spdif1m0_tx>;
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};
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&spdif_tx1_dc {
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status = "okay";
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};
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&spdif_tx1_sound {
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status = "okay";
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};
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&usbdp_phy0 {
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status = "disabled";
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};
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&usbdp_phy0_dp {
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status = "disabled";
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};
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&usbdp_phy0_u3 {
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status = "disabled";
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};
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&usbdrd_dwc3_0 {
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dr_mode = "peripheral";
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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maximum-speed = "high-speed";
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};
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&usbhost3_0 {
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status = "disabled";
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};
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&usbhost_dwc3_0 {
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status = "disabled";
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};
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