/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Low level suspend code for AM33XX SoCs
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*
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* Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/
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* Dave Gerlach, Vaibhav Bedia
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*/
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#include <linux/linkage.h>
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#include <linux/platform_data/pm33xx.h>
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#include <linux/ti-emif-sram.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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#include "iomap.h"
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#include "cm33xx.h"
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#include "pm-asm-offsets.h"
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#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
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#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
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#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
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/* replicated define because linux/bitops.h cannot be included in assembly */
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#define BIT(nr) (1 << (nr))
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.arm
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.arch armv7-a
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.align 3
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ENTRY(am33xx_do_wfi)
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stmfd sp!, {r4 - r11, lr} @ save registers on stack
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/* Save wfi_flags arg to data space */
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mov r4, r0
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adr r3, am33xx_pm_ro_sram_data
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ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
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str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
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/* Only flush cache is we know we are losing MPU context */
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tst r4, #WFI_FLAG_FLUSH_CACHE
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beq cache_skip_flush
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/*
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* Flush all data from the L1 and L2 data cache before disabling
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* SCTLR.C bit.
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*/
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ldr r1, kernel_flush
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blx r1
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Invalidate L1 and L2 data cache.
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*/
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ldr r1, kernel_flush
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blx r1
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adr r3, am33xx_pm_ro_sram_data
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ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
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ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
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cache_skip_flush:
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/* Check if we want self refresh */
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tst r4, #WFI_FLAG_SELF_REFRESH
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beq emif_skip_enter_sr
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adr r9, am33xx_emif_sram_table
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ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
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blx r3
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emif_skip_enter_sr:
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/* Only necessary if PER is losing context */
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tst r4, #WFI_FLAG_SAVE_EMIF
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beq emif_skip_save
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ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
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blx r3
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emif_skip_save:
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/* Only can disable EMIF if we have entered self refresh */
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tst r4, #WFI_FLAG_SELF_REFRESH
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beq emif_skip_disable
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/* Disable EMIF */
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ldr r1, virt_emif_clkctrl
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ldr r2, [r1]
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bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
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str r2, [r1]
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ldr r1, virt_emif_clkctrl
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wait_emif_disable:
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ldr r2, [r1]
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mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
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cmp r2, r3
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bne wait_emif_disable
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emif_skip_disable:
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tst r4, #WFI_FLAG_WAKE_M3
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beq wkup_m3_skip
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/*
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* For the MPU WFI to be registered as an interrupt
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* to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
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* to DISABLED
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*/
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ldr r1, virt_mpu_clkctrl
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ldr r2, [r1]
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bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
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str r2, [r1]
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wkup_m3_skip:
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/*
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* Execute an ISB instruction to ensure that all of the
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* CP15 register changes have been committed.
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*/
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isb
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/*
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* Execute a barrier instruction to ensure that all cache,
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* TLB and branch predictor maintenance operations issued
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* have completed.
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*/
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dsb
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dmb
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/*
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* Execute a WFI instruction and wait until the
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* STANDBYWFI output is asserted to indicate that the
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* CPU is in idle and low power state. CPU can specualatively
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* prefetch the instructions so add NOPs after WFI. Thirteen
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* NOPs as per Cortex-A8 pipeline.
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*/
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wfi
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/* We come here in case of an abort due to a late interrupt */
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/* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */
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ldr r1, virt_mpu_clkctrl
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mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
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str r2, [r1]
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/* Re-enable EMIF */
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ldr r1, virt_emif_clkctrl
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mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
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str r2, [r1]
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wait_emif_enable:
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ldr r3, [r1]
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cmp r2, r3
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bne wait_emif_enable
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/* Only necessary if PER is losing context */
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tst r4, #WFI_FLAG_SELF_REFRESH
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beq emif_skip_exit_sr_abt
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adr r9, am33xx_emif_sram_table
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ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
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blx r1
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emif_skip_exit_sr_abt:
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tst r4, #WFI_FLAG_FLUSH_CACHE
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beq cache_skip_restore
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/*
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* Set SCTLR.C bit to allow data cache allocation
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*/
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #(1 << 2) @ Enable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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cache_skip_restore:
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/* Let the suspend code know about the abort */
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mov r0, #1
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ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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ENDPROC(am33xx_do_wfi)
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.align
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ENTRY(am33xx_resume_offset)
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.word . - am33xx_do_wfi
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ENTRY(am33xx_resume_from_deep_sleep)
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/* Re-enable EMIF */
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ldr r0, phys_emif_clkctrl
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mov r1, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
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str r1, [r0]
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wait_emif_enable1:
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ldr r2, [r0]
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cmp r1, r2
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bne wait_emif_enable1
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adr r9, am33xx_emif_sram_table
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ldr r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
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blx r1
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ldr r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
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blx r1
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resume_to_ddr:
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/* We are back. Branch to the common CPU resume routine */
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mov r0, #0
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ldr pc, resume_addr
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ENDPROC(am33xx_resume_from_deep_sleep)
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/*
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* Local variables
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*/
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.align
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kernel_flush:
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.word v7_flush_dcache_all
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virt_mpu_clkctrl:
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.word AM33XX_CM_MPU_MPU_CLKCTRL
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virt_emif_clkctrl:
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.word AM33XX_CM_PER_EMIF_CLKCTRL
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phys_emif_clkctrl:
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.word (AM33XX_CM_BASE + AM33XX_CM_PER_MOD + \
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AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET)
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.align 3
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/* DDR related defines */
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am33xx_emif_sram_table:
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.space EMIF_PM_FUNCTIONS_SIZE
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ENTRY(am33xx_pm_sram)
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.word am33xx_do_wfi
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.word am33xx_do_wfi_sz
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.word am33xx_resume_offset
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.word am33xx_emif_sram_table
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.word am33xx_pm_ro_sram_data
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resume_addr:
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.word cpu_resume - PAGE_OFFSET + 0x80000000
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.align 3
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ENTRY(am33xx_pm_ro_sram_data)
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.space AMX3_PM_RO_SRAM_DATA_SIZE
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ENTRY(am33xx_do_wfi_sz)
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.word . - am33xx_do_wfi
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