1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
| /* SPDX-License-Identifier: GPL-2.0-only */
| /*
| * arch/arm/include/debug/icedcc.S
| *
| * Copyright (C) 1994-1999 Russell King
| */
|
| @@ debug using ARM EmbeddedICE DCC channel
|
| .macro addruart, rp, rv, tmp
| .endm
|
| #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
|
| .macro senduart, rd, rx
| mcr p14, 0, \rd, c0, c5, 0
| .endm
|
| .macro busyuart, rd, rx
| 1001:
| mrc p14, 0, \rx, c0, c1, 0
| tst \rx, #0x20000000
| beq 1001b
| .endm
|
| .macro waituartcts, rd, rx
| .endm
|
| .macro waituarttxrdy, rd, rx
| mov \rd, #0x2000000
| 1001:
| subs \rd, \rd, #1
| bmi 1002f
| mrc p14, 0, \rx, c0, c1, 0
| tst \rx, #0x20000000
| bne 1001b
| 1002:
| .endm
|
| #elif defined(CONFIG_CPU_XSCALE)
|
| .macro senduart, rd, rx
| mcr p14, 0, \rd, c8, c0, 0
| .endm
|
| .macro busyuart, rd, rx
| 1001:
| mrc p14, 0, \rx, c14, c0, 0
| tst \rx, #0x10000000
| beq 1001b
| .endm
|
| .macro waituartcts, rd, rx
| .endm
|
| .macro waituarttxrdy, rd, rx
| mov \rd, #0x10000000
| 1001:
| subs \rd, \rd, #1
| bmi 1002f
| mrc p14, 0, \rx, c14, c0, 0
| tst \rx, #0x10000000
| bne 1001b
| 1002:
| .endm
|
| #else
|
| .macro senduart, rd, rx
| mcr p14, 0, \rd, c1, c0, 0
| .endm
|
| .macro busyuart, rd, rx
| 1001:
| mrc p14, 0, \rx, c0, c0, 0
| tst \rx, #2
| beq 1001b
|
| .endm
|
| .macro waituartcts, rd, rx
| .endm
|
| .macro waituarttxrdy, rd, rx
| mov \rd, #0x2000000
| 1001:
| subs \rd, \rd, #1
| bmi 1002f
| mrc p14, 0, \rx, c0, c0, 0
| tst \rx, #2
| bne 1001b
| 1002:
| .endm
|
| #endif /* CONFIG_CPU_V6 */
|
|