/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip Vehicle driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#ifndef _VEHICLE_SAMSUNG_DCPHY_COMMON_H_
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#define _VEHICLE_SAMSUNG_DCPHY_COMMON_H_
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#define MAX_NUM_CSI2_DPHY (0x2)
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/*redefine samsung_mipi_dcphy info*/
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struct samsung_mipi_dcphy {
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struct device *dev;
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struct clk *ref_clk;
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struct clk *pclk;
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struct regmap *regmap;
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struct regmap *grf_regmap;
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struct reset_control *m_phy_rst;
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struct reset_control *s_phy_rst;
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struct reset_control *apb_rst;
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struct reset_control *grf_apb_rst;
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struct mutex mutex;
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struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
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atomic_t stream_cnt;
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int dphy_dev_num;
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bool c_option;
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unsigned int lanes;
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struct {
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unsigned long long rate;
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u8 prediv;
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u16 fbdiv;
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long dsm;
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u8 scaler;
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bool ssc_en;
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u8 mfr;
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u8 mrr;
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} pll;
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int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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/*for vehicle*/
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struct csi2_dphy_hw *dphy_vehicle[MAX_NUM_CSI2_DPHY];
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int dphy_vehicle_num;
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};
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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/*samsung mipi dcphy register*/
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#define BIAS_CON0 0x0000
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#define BIAS_CON1 0x0004
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#define BIAS_CON2 0x0008
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#define BIAS_CON4 0x0010
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#define I_MUX_SEL_MASK GENMASK(6, 5)
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#define I_MUX_SEL(x) UPDATE(x, 6, 5)
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#define PLL_CON0 0x0100
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#define PLL_EN BIT(12)
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#define S_MASK GENMASK(10, 8)
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#define S(x) UPDATE(x, 10, 8)
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#define P_MASK GENMASK(5, 0)
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#define P(x) UPDATE(x, 5, 0)
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#define PLL_CON1 0x0104
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#define PLL_CON2 0x0108
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#define M_MASK GENMASK(9, 0)
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#define M(x) UPDATE(x, 9, 0)
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#define PLL_CON3 0x010c
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#define MRR_MASK GENMASK(13, 8)
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#define MRR(x) UPDATE(x, 13, 8)
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#define MFR_MASK GENMASK(7, 0)
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#define MFR(x) UPDATE(x, 7, 0)
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#define PLL_CON4 0x0110
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#define SSCG_EN BIT(11)
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#define PLL_CON5 0x0114
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#define RESET_N_SEL BIT(10)
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#define PLL_ENABLE_SEL BIT(8)
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#define PLL_CON6 0x0118
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#define PLL_CON7 0x011c
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#define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
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#define PLL_CON8 0x0120
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#define PLL_STB_CNT(x) UPDATE(x, 15, 0)
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#define PLL_STAT0 0x0140
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#define PLL_LOCK BIT(0)
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#define DPHY_MC_GNR_CON0 0x0300
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#define PHY_READY BIT(1)
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#define PHY_ENABLE BIT(0)
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#define DPHY_MC_GNR_CON1 0x0304
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#define T_PHY_READY(x) UPDATE(x, 15, 0)
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#define DPHY_MC_ANA_CON0 0x0308
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#define DPHY_MC_ANA_CON1 0x030c
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#define DPHY_MC_ANA_CON2 0x0310
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#define HS_VREG_AMP_ICON(x) UPDATE(x, 1, 0)
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#define DPHY_MC_TIME_CON0 0x0330
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#define HSTX_CLK_SEL BIT(12)
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#define T_LPX(x) UPDATE(x, 11, 4)
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#define DPHY_MC_TIME_CON1 0x0334
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#define T_CLK_ZERO(x) UPDATE(x, 15, 8)
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#define T_CLK_PREPARE(x) UPDATE(x, 7, 0)
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#define DPHY_MC_TIME_CON2 0x0338
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#define T_HS_EXIT(x) UPDATE(x, 15, 8)
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#define T_CLK_TRAIL(x) UPDATE(x, 7, 0)
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#define DPHY_MC_TIME_CON3 0x033c
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#define T_CLK_POST(x) UPDATE(x, 7, 0)
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#define DPHY_MC_TIME_CON4 0x0340
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#define T_ULPS_EXIT(x) UPDATE(x, 9, 0)
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#define DPHY_MC_DESKEW_CON0 0x0350
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#define SKEW_CAL_RUN_TIME(x) UPDATE(x, 15, 12)
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#define SKEW_CAL_INIT_RUN_TIME(x) UPDATE(x, 11, 8)
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#define SKEW_CAL_INIT_WAIT_TIME(x) UPDATE(x, 7, 4)
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#define SKEW_CAL_EN BIT(0)
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#define COMBO_MD0_GNR_CON0 0x0400
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#define COMBO_MD0_GNR_CON1 0x0404
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#define COMBO_MD0_ANA_CON0 0x0408
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#define COMBO_MD0_ANA_CON1 0x040C
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#define COMBO_MD0_ANA_CON2 0x0410
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#define COMBO_MD0_TIME_CON0 0x0430
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#define COMBO_MD0_TIME_CON1 0x0434
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#define COMBO_MD0_TIME_CON2 0x0438
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#define COMBO_MD0_TIME_CON3 0x043C
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#define COMBO_MD0_TIME_CON4 0x0440
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#define COMBO_MD0_DATA_CON0 0x0444
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#define COMBO_MD1_GNR_CON0 0x0500
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#define COMBO_MD1_GNR_CON1 0x0504
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#define COMBO_MD1_ANA_CON0 0x0508
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#define COMBO_MD1_ANA_CON1 0x050c
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#define COMBO_MD1_ANA_CON2 0x0510
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#define COMBO_MD1_TIME_CON0 0x0530
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#define COMBO_MD1_TIME_CON1 0x0534
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#define COMBO_MD1_TIME_CON2 0x0538
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#define COMBO_MD1_TIME_CON3 0x053C
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#define COMBO_MD1_TIME_CON4 0x0540
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#define COMBO_MD1_DATA_CON0 0x0544
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#define COMBO_MD2_GNR_CON0 0x0600
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#define COMBO_MD2_GNR_CON1 0x0604
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#define COMBO_MD2_ANA_CON0 0X0608
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#define COMBO_MD2_ANA_CON1 0X060C
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#define COMBO_MD2_ANA_CON2 0X0610
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#define COMBO_MD2_TIME_CON0 0x0630
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#define COMBO_MD2_TIME_CON1 0x0634
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#define COMBO_MD2_TIME_CON2 0x0638
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#define COMBO_MD2_TIME_CON3 0x063C
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#define COMBO_MD2_TIME_CON4 0x0640
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#define COMBO_MD2_DATA_CON0 0x0644
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#define DPHY_MD3_GNR_CON0 0x0700
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#define DPHY_MD3_GNR_CON1 0x0704
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#define DPHY_MD3_ANA_CON0 0X0708
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#define DPHY_MD3_ANA_CON1 0X070C
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#define DPHY_MD3_ANA_CON2 0X0710
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#define DPHY_MD3_TIME_CON0 0x0730
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#define DPHY_MD3_TIME_CON1 0x0734
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#define DPHY_MD3_TIME_CON2 0x0738
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#define DPHY_MD3_TIME_CON3 0x073C
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#define DPHY_MD3_TIME_CON4 0x0740
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#define DPHY_MD3_DATA_CON0 0x0744
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#define T_LP_EXIT_SKEW(x) UPDATE(x, 3, 2)
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#define T_LP_ENTRY_SKEW(x) UPDATE(x, 1, 0)
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#define T_HS_ZERO(x) UPDATE(x, 15, 8)
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#define T_HS_PREPARE(x) UPDATE(x, 7, 0)
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#define T_HS_EXIT(x) UPDATE(x, 15, 8)
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#define T_HS_TRAIL(x) UPDATE(x, 7, 0)
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#define T_TA_GET(x) UPDATE(x, 7, 4)
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#define T_TA_GO(x) UPDATE(x, 3, 0)
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/* MIPI_CDPHY_GRF registers */
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#define MIPI_DCPHY_GRF_CON0 0x0000
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#define S_CPHY_MODE HIWORD_UPDATE(1, 3, 3)
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#define M_CPHY_MODE HIWORD_UPDATE(1, 0, 0)
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#define MAX_DPHY_BW 4500000L
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#define MAX_CPHY_BW 2000000L
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#define RX_CLK_THS_SETTLE (0xb30)
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#define RX_LANE0_THS_SETTLE (0xC30)
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#define RX_LANE0_ERR_SOT_SYNC (0xC34)
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#define RX_LANE1_THS_SETTLE (0xD30)
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#define RX_LANE1_ERR_SOT_SYNC (0xD34)
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#define RX_LANE2_THS_SETTLE (0xE30)
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#define RX_LANE2_ERR_SOT_SYNC (0xE34)
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#define RX_LANE3_THS_SETTLE (0xF30)
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#define RX_LANE3_ERR_SOT_SYNC (0xF34)
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#define RX_CLK_LANE_ENABLE (0xB00)
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#define RX_DATA_LANE0_ENABLE (0xC00)
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#define RX_DATA_LANE1_ENABLE (0xD00)
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#define RX_DATA_LANE2_ENABLE (0xE00)
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#define RX_DATA_LANE3_ENABLE (0xF00)
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#define RX_S0C_GNR_CON1 (0xB04)
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#define RX_S0C_ANA_CON1 (0xB0c)
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#define RX_S0C_ANA_CON2 (0xB10)
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#define RX_S0C_ANA_CON3 (0xB14)
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#define RX_COMBO_S0D0_GNR_CON1 (0xC04)
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#define RX_COMBO_S0D0_ANA_CON1 (0xC0c)
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#define RX_COMBO_S0D0_ANA_CON2 (0xC10)
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#define RX_COMBO_S0D0_ANA_CON3 (0xC14)
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#define RX_COMBO_S0D0_ANA_CON6 (0xC20)
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#define RX_COMBO_S0D0_ANA_CON7 (0xC24)
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#define RX_COMBO_S0D0_DESKEW_CON0 (0xC40)
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#define RX_COMBO_S0D0_DESKEW_CON2 (0xC48)
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#define RX_COMBO_S0D0_DESKEW_CON4 (0xC50)
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#define RX_COMBO_S0D0_CRC_CON1 (0xC64)
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#define RX_COMBO_S0D0_CRC_CON2 (0xC68)
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#define RX_COMBO_S0D1_GNR_CON1 (0xD04)
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#define RX_COMBO_S0D1_ANA_CON1 (0xD0c)
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#define RX_COMBO_S0D1_ANA_CON2 (0xD10)
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#define RX_COMBO_S0D1_ANA_CON3 (0xD14)
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#define RX_COMBO_S0D1_ANA_CON6 (0xD20)
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#define RX_COMBO_S0D1_ANA_CON7 (0xD24)
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#define RX_COMBO_S0D1_DESKEW_CON0 (0xD40)
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#define RX_COMBO_S0D1_DESKEW_CON2 (0xD48)
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#define RX_COMBO_S0D1_DESKEW_CON4 (0xD50)
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#define RX_COMBO_S0D1_CRC_CON1 (0xD64)
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#define RX_COMBO_S0D1_CRC_CON2 (0xD68)
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#define RX_COMBO_S0D2_GNR_CON1 (0xE04)
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#define RX_COMBO_S0D2_ANA_CON1 (0xE0c)
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#define RX_COMBO_S0D2_ANA_CON2 (0xE10)
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#define RX_COMBO_S0D2_ANA_CON3 (0xE14)
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#define RX_COMBO_S0D2_ANA_CON6 (0xE20)
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#define RX_COMBO_S0D2_ANA_CON7 (0xE24)
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#define RX_COMBO_S0D2_DESKEW_CON0 (0xE40)
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#define RX_COMBO_S0D2_DESKEW_CON2 (0xE48)
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#define RX_COMBO_S0D2_DESKEW_CON4 (0xE50)
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#define RX_COMBO_S0D2_CRC_CON1 (0xE64)
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#define RX_COMBO_S0D2_CRC_CON2 (0xE68)
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#define RX_S0D3_GNR_CON1 (0xF04)
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#define RX_S0D3_ANA_CON1 (0xF0c)
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#define RX_S0D3_ANA_CON2 (0xF10)
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#define RX_S0D3_ANA_CON3 (0xF14)
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#define RX_S0D3_DESKEW_CON0 (0xF40)
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#define RX_S0D3_DESKEW_CON2 (0xF48)
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#define RX_S0D3_DESKEW_CON4 (0xF50)
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#endif
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