/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#ifndef __RTL8712_SPEC_H__
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#define __RTL8712_SPEC_H__
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#define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/
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#define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/
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#define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/
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#define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/
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#define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/
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#define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/
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#define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/
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#define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/
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#define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/
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#define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/
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#define RTL8712_IOBASE_FW2HW 0x102A0000 /*IOBASE_FW2HW*/
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#define RTL8712_IOBASE_ACCESS_PHYREG 0x102B0000 /*IOBASE_ACCESS_PHYREG*/
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#define RTL8712_IOBASE_FF 0x10300000 /*IOBASE_FIFO 0x1031000~0x103AFFFF*/
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/*IOREG Offset for 8712*/
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#define RTL8712_SYSCFG_ RTL8712_IOBASE_IOREG
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#define RTL8712_CMDCTRL_ (RTL8712_IOBASE_IOREG + 0x40)
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#define RTL8712_MACIDSETTING_ (RTL8712_IOBASE_IOREG + 0x50)
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#define RTL8712_TIMECTRL_ (RTL8712_IOBASE_IOREG + 0x80)
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#define RTL8712_FIFOCTRL_ (RTL8712_IOBASE_IOREG + 0xA0)
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#define RTL8712_RATECTRL_ (RTL8712_IOBASE_IOREG + 0x160)
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#define RTL8712_EDCASETTING_ (RTL8712_IOBASE_IOREG + 0x1D0)
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#define RTL8712_WMAC_ (RTL8712_IOBASE_IOREG + 0x200)
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#define RTL8712_SECURITY_ (RTL8712_IOBASE_IOREG + 0x240)
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#define RTL8712_POWERSAVE_ (RTL8712_IOBASE_IOREG + 0x260)
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#define RTL8712_GP_ (RTL8712_IOBASE_IOREG + 0x2E0)
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#define RTL8712_INTERRUPT_ (RTL8712_IOBASE_IOREG + 0x300)
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#define RTL8712_DEBUGCTRL_ (RTL8712_IOBASE_IOREG + 0x310)
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#define RTL8712_OFFLOAD_ (RTL8712_IOBASE_IOREG + 0x2D0)
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/*FIFO for 8712*/
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#define RTL8712_DMA_BCNQ (RTL8712_IOBASE_FF + 0x10000)
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#define RTL8712_DMA_MGTQ (RTL8712_IOBASE_FF + 0x20000)
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#define RTL8712_DMA_BMCQ (RTL8712_IOBASE_FF + 0x30000)
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#define RTL8712_DMA_VOQ (RTL8712_IOBASE_FF + 0x40000)
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#define RTL8712_DMA_VIQ (RTL8712_IOBASE_FF + 0x50000)
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#define RTL8712_DMA_BEQ (RTL8712_IOBASE_FF + 0x60000)
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#define RTL8712_DMA_BKQ (RTL8712_IOBASE_FF + 0x70000)
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#define RTL8712_DMA_RX0FF (RTL8712_IOBASE_FF + 0x80000)
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#define RTL8712_DMA_H2CCMD (RTL8712_IOBASE_FF + 0x90000)
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#define RTL8712_DMA_C2HCMD (RTL8712_IOBASE_FF + 0xA0000)
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/*------------------------------*/
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/*BIT 16 15*/
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#define DID_SDIO_LOCAL 0 /* 0 0*/
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#define DID_WLAN_IOREG 1 /* 0 1*/
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#define DID_WLAN_FIFO 3 /* 1 1*/
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#define DID_UNDEFINE (-1)
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#define CMD_ADDR_MAPPING_SHIFT 2 /*SDIO CMD ADDR MAPPING,
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*shift 2 bit for match
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* offset[14:2]
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*/
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/*Offset for SDIO LOCAL*/
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#define OFFSET_SDIO_LOCAL 0x0FFF
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/*Offset for WLAN IOREG*/
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#define OFFSET_WLAN_IOREG 0x0FFF
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/*Offset for WLAN FIFO*/
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#define OFFSET_TX_BCNQ 0x0300
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#define OFFSET_TX_HIQ 0x0310
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#define OFFSET_TX_CMDQ 0x0320
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#define OFFSET_TX_MGTQ 0x0330
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#define OFFSET_TX_HCCAQ 0x0340
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#define OFFSET_TX_VOQ 0x0350
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#define OFFSET_TX_VIQ 0x0360
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#define OFFSET_TX_BEQ 0x0370
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#define OFFSET_TX_BKQ 0x0380
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#define OFFSET_RX_RX0FFQ 0x0390
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#define OFFSET_RX_C2HFFQ 0x03A0
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#define BK_QID_01 1
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#define BK_QID_02 2
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#define BE_QID_01 0
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#define BE_QID_02 3
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#define VI_QID_01 4
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#define VI_QID_02 5
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#define VO_QID_01 6
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#define VO_QID_02 7
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#define HCCA_QID_01 8
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#define HCCA_QID_02 9
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#define HCCA_QID_03 10
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#define HCCA_QID_04 11
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#define HCCA_QID_05 12
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#define HCCA_QID_06 13
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#define HCCA_QID_07 14
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#define HCCA_QID_08 15
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#define HI_QID 17
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#define CMD_QID 19
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#define MGT_QID 18
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#define BCN_QID 16
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#include "rtl8712_regdef.h"
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#include "rtl8712_bitdef.h"
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#include "basic_types.h"
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#endif /* __RTL8712_SPEC_H__ */
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