/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#ifndef __RTL8712_GP_BITDEF_H__
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#define __RTL8712_GP_BITDEF_H__
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/*GPIO_CTRL*/
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#define _GPIO_MOD_MSK 0xFF000000
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#define _GPIO_MOD_SHT 24
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#define _GPIO_IO_SEL_MSK 0x00FF0000
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#define _GPIO_IO_SEL_SHT 16
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#define _GPIO_OUT_MSK 0x0000FF00
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#define _GPIO_OUT_SHT 8
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#define _GPIO_IN_MSK 0x000000FF
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#define _GPIO_IN_SHT 0
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/*SYS_PINMUX_CFG*/
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#define _GPIOSEL_MSK 0x0003
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#define _GPIOSEL_SHT 0
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/*LED_CFG*/
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#define _LED1SV BIT(7)
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#define _LED1CM_MSK 0x0070
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#define _LED1CM_SHT 4
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#define _LED0SV BIT(3)
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#define _LED0CM_MSK 0x0007
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#define _LED0CM_SHT 0
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/*PHY_REG*/
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#define _HST_RDRDY_SHT 0
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#define _HST_RDRDY_MSK 0xFF
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#define _HST_RDRDY BIT(_HST_RDRDY_SHT)
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#define _CPU_WTBUSY_SHT 1
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#define _CPU_WTBUSY_MSK 0xFF
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#define _CPU_WTBUSY BIT(_CPU_WTBUSY_SHT)
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/* 11. General Purpose Registers (Offset: 0x02E0 - 0x02FF)*/
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/* 8192S GPIO Config Setting (offset 0x2F1, 1 byte)*/
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/*----------------------------------------------------------------------------*/
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#define GPIOMUX_EN BIT(3) /* When this bit is set to "1",
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* GPIO PINs will switch to MAC
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* GPIO Function
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*/
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#define GPIOSEL_GPIO 0 /* UART or JTAG or pure GPIO*/
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#define GPIOSEL_PHYDBG 1 /* PHYDBG*/
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#define GPIOSEL_BT 2 /* BT_coex*/
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#define GPIOSEL_WLANDBG 3 /* WLANDBG*/
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#define GPIOSEL_GPIO_MASK (~(BIT(0) | BIT(1)))
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/* HW Radio OFF switch (GPIO BIT) */
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#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
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#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
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#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
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#endif /*__RTL8712_GP_BITDEF_H__*/
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