/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __SYSTEM_LOCAL_H_INCLUDED__
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#define __SYSTEM_LOCAL_H_INCLUDED__
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#ifdef HRT_ISP_CSS_CUSTOM_HOST
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#ifndef HRT_USE_VIR_ADDRS
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#define HRT_USE_VIR_ADDRS
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#endif
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#endif
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#include "system_global.h"
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/* This interface is deprecated */
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#include "hive_types.h"
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/*
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* Cell specific address maps
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*/
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#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
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/* ISP */
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extern const hrt_address ISP_CTRL_BASE[N_ISP_ID];
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extern const hrt_address ISP_DMEM_BASE[N_ISP_ID];
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extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID];
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/* SP */
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extern const hrt_address SP_CTRL_BASE[N_SP_ID];
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extern const hrt_address SP_DMEM_BASE[N_SP_ID];
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/* MMU */
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extern const hrt_address MMU_BASE[N_MMU_ID];
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/* DMA */
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extern const hrt_address DMA_BASE[N_DMA_ID];
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extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID];
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/* IRQ */
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extern const hrt_address IRQ_BASE[N_IRQ_ID];
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/* GDC */
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extern const hrt_address GDC_BASE[N_GDC_ID];
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/* FIFO_MONITOR (not a subset of GP_DEVICE) */
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extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID];
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/* GP_DEVICE (single base for all separate GP_REG instances) */
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extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID];
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/*GP TIMER , all timer registers are inter-twined,
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* so, having multiple base addresses for
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* different timers does not help*/
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extern const hrt_address GP_TIMER_BASE;
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/* GPIO */
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extern const hrt_address GPIO_BASE[N_GPIO_ID];
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/* TIMED_CTRL */
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extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID];
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/* INPUT_FORMATTER */
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extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID];
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/* INPUT_SYSTEM */
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extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID];
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/* RX, the MIPI lane control regs start at offset 0 */
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extern const hrt_address RX_BASE[N_RX_ID];
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/* IBUF_CTRL, part of the Input System 2401 */
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extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID];
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/* ISYS IRQ Controllers, part of the Input System 2401 */
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extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID];
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/* CSI FE, part of the Input System 2401 */
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extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID];
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/* CSI BE, part of the Input System 2401 */
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extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID];
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/* PIXEL Generator, part of the Input System 2401 */
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extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID];
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/* Stream2MMIO, part of the Input System 2401 */
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extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID];
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#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */
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