/* SPDX-License-Identifier: GPL-2.0 */
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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*/
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#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
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#define __SYSTEM_GLOBAL_H_INCLUDED__
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/*
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* Create a list of HAS and IS properties that defines the system
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* Those are common for both ISP2400 and ISP2401
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*
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* The configuration assumes the following
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* - The system is hetereogeneous; Multiple cells and devices classes
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* - The cell and device instances are homogeneous, each device type
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* belongs to the same class
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* - Device instances supporting a subset of the class capabilities are
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* allowed
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*
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* We could manage different device classes through the enumerated
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* lists (C) or the use of classes (C++), but that is presently not
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* fully supported
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*
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* N.B. the 3 input formatters are of 2 different classess
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*/
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/* per-frame parameter handling support */
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#define SH_CSS_ENABLE_PER_FRAME_PARAMS
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#define DMA_DDR_TO_VAMEM_WORKAROUND
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#define DMA_DDR_TO_HMEM_WORKAROUND
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/*
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* The longest allowed (uninteruptible) bus transfer, does not
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* take stalling into account
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*/
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#define HIVE_ISP_MAX_BURST_LENGTH 1024
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/*
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* Maximum allowed burst length in words for the ISP DMA
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* This value is set to 2 to prevent the ISP DMA from blocking
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* the bus for too long; as the input system can only buffer
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* 2 lines on Moorefield and Cherrytrail, the input system buffers
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* may overflow if blocked for too long (BZ 2726).
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*/
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#define ISP2400_DMA_MAX_BURST_LENGTH 128
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#define ISP2401_DMA_MAX_BURST_LENGTH 2
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#include <hive_isp_css_defs.h>
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#include <type_support.h>
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/* This interface is deprecated */
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#include "hive_types.h"
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/*
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* Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
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*/
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#define HRT_VADDRESS_WIDTH 32
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#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
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#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
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/* The main bus connecting all devices */
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#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
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#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
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typedef u32 hrt_bus_align_t;
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/*
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* Enumerate the devices, device access through the API is by ID,
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* through the DLI by address. The enumerator terminators are used
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* to size the wiring arrays and as an exception value.
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*/
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typedef enum {
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DDR0_ID = 0,
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N_DDR_ID
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} ddr_ID_t;
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typedef enum {
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ISP0_ID = 0,
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N_ISP_ID
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} isp_ID_t;
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typedef enum {
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SP0_ID = 0,
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N_SP_ID
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} sp_ID_t;
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typedef enum {
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MMU0_ID = 0,
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MMU1_ID,
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N_MMU_ID
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} mmu_ID_t;
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typedef enum {
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DMA0_ID = 0,
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N_DMA_ID
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} dma_ID_t;
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typedef enum {
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GDC0_ID = 0,
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GDC1_ID,
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N_GDC_ID
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} gdc_ID_t;
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/* this extra define is needed because we want to use it also
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in the preprocessor, and that doesn't work with enums.
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*/
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#define N_GDC_ID_CPP 2
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typedef enum {
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VAMEM0_ID = 0,
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VAMEM1_ID,
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VAMEM2_ID,
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N_VAMEM_ID
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} vamem_ID_t;
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typedef enum {
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BAMEM0_ID = 0,
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N_BAMEM_ID
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} bamem_ID_t;
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typedef enum {
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HMEM0_ID = 0,
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N_HMEM_ID
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} hmem_ID_t;
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typedef enum {
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IRQ0_ID = 0, /* GP IRQ block */
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IRQ1_ID, /* Input formatter */
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IRQ2_ID, /* input system */
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IRQ3_ID, /* input selector */
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N_IRQ_ID
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} irq_ID_t;
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typedef enum {
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FIFO_MONITOR0_ID = 0,
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N_FIFO_MONITOR_ID
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} fifo_monitor_ID_t;
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typedef enum {
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GP_DEVICE0_ID = 0,
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N_GP_DEVICE_ID
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} gp_device_ID_t;
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typedef enum {
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GP_TIMER0_ID = 0,
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GP_TIMER1_ID,
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GP_TIMER2_ID,
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GP_TIMER3_ID,
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GP_TIMER4_ID,
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GP_TIMER5_ID,
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GP_TIMER6_ID,
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GP_TIMER7_ID,
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N_GP_TIMER_ID
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} gp_timer_ID_t;
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typedef enum {
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GPIO0_ID = 0,
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N_GPIO_ID
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} gpio_ID_t;
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typedef enum {
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TIMED_CTRL0_ID = 0,
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N_TIMED_CTRL_ID
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} timed_ctrl_ID_t;
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typedef enum {
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INPUT_FORMATTER0_ID = 0,
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INPUT_FORMATTER1_ID,
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INPUT_FORMATTER2_ID,
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INPUT_FORMATTER3_ID,
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N_INPUT_FORMATTER_ID
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} input_formatter_ID_t;
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/* The IF RST is outside the IF */
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#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
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#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
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#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
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#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
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#define INPUT_FORMATTER0_SRST_MASK 0x0001
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#define INPUT_FORMATTER1_SRST_MASK 0x0002
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#define INPUT_FORMATTER2_SRST_MASK 0x0004
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#define INPUT_FORMATTER3_SRST_MASK 0x0008
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typedef enum {
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INPUT_SYSTEM0_ID = 0,
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N_INPUT_SYSTEM_ID
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} input_system_ID_t;
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typedef enum {
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RX0_ID = 0,
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N_RX_ID
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} rx_ID_t;
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enum mipi_port_id {
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MIPI_PORT0_ID = 0,
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MIPI_PORT1_ID,
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MIPI_PORT2_ID,
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N_MIPI_PORT_ID
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};
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#define N_RX_CHANNEL_ID 4
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/* Generic port enumeration with an internal port type ID */
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typedef enum {
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CSI_PORT0_ID = 0,
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CSI_PORT1_ID,
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CSI_PORT2_ID,
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TPG_PORT0_ID,
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PRBS_PORT0_ID,
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FIFO_PORT0_ID,
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MEMORY_PORT0_ID,
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N_INPUT_PORT_ID
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} input_port_ID_t;
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typedef enum {
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CAPTURE_UNIT0_ID = 0,
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CAPTURE_UNIT1_ID,
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CAPTURE_UNIT2_ID,
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ACQUISITION_UNIT0_ID,
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DMA_UNIT0_ID,
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CTRL_UNIT0_ID,
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GPREGS_UNIT0_ID,
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FIFO_UNIT0_ID,
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IRQ_UNIT0_ID,
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N_SUB_SYSTEM_ID
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} sub_system_ID_t;
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#define N_CAPTURE_UNIT_ID 3
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#define N_ACQUISITION_UNIT_ID 1
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#define N_CTRL_UNIT_ID 1
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enum ia_css_isp_memories {
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IA_CSS_ISP_PMEM0 = 0,
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IA_CSS_ISP_DMEM0,
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IA_CSS_ISP_VMEM0,
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IA_CSS_ISP_VAMEM0,
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IA_CSS_ISP_VAMEM1,
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IA_CSS_ISP_VAMEM2,
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IA_CSS_ISP_HMEM0,
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IA_CSS_SP_DMEM0,
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IA_CSS_DDR,
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N_IA_CSS_MEMORIES
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};
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#define IA_CSS_NUM_MEMORIES 9
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/* For driver compatibility */
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#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
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/*
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* ISP2401 specific enums
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*/
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typedef enum {
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ISYS_IRQ0_ID = 0, /* port a */
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ISYS_IRQ1_ID, /* port b */
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ISYS_IRQ2_ID, /* port c */
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N_ISYS_IRQ_ID
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} isys_irq_ID_t;
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/*
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* Input-buffer Controller.
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*/
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typedef enum {
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IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
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IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
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IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
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N_IBUF_CTRL_ID
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} ibuf_ctrl_ID_t;
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/* end of Input-buffer Controller */
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/*
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* Stream2MMIO.
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*/
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typedef enum {
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STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
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STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
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STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
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N_STREAM2MMIO_ID
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} stream2mmio_ID_t;
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typedef enum {
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/*
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* Stream2MMIO 0 has 8 SIDs that are indexed by
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* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
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*
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* Stream2MMIO 1 has 4 SIDs that are indexed by
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* [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
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*
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* Stream2MMIO 2 has 4 SIDs that are indexed by
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* [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
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*/
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STREAM2MMIO_SID0_ID = 0,
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STREAM2MMIO_SID1_ID,
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STREAM2MMIO_SID2_ID,
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STREAM2MMIO_SID3_ID,
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STREAM2MMIO_SID4_ID,
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STREAM2MMIO_SID5_ID,
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STREAM2MMIO_SID6_ID,
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STREAM2MMIO_SID7_ID,
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N_STREAM2MMIO_SID_ID
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} stream2mmio_sid_ID_t;
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/* end of Stream2MMIO */
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/**
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* Input System 2401: CSI-MIPI recevier.
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*/
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typedef enum {
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CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
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CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
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CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
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N_CSI_RX_BACKEND_ID
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} csi_rx_backend_ID_t;
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typedef enum {
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CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
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CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
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CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
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#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
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} csi_rx_frontend_ID_t;
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typedef enum {
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CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
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CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
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CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
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CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
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N_CSI_RX_DLANE_ID
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} csi_rx_fe_dlane_ID_t;
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/* end of CSI-MIPI receiver */
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typedef enum {
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ISYS2401_DMA0_ID = 0,
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N_ISYS2401_DMA_ID
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} isys2401_dma_ID_t;
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/**
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* Pixel-generator. ("system_global.h")
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*/
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typedef enum {
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PIXELGEN0_ID = 0,
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PIXELGEN1_ID,
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PIXELGEN2_ID,
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N_PIXELGEN_ID
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} pixelgen_ID_t;
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/* end of pixel-generator. ("system_global.h") */
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typedef enum {
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INPUT_SYSTEM_CSI_PORT0_ID = 0,
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INPUT_SYSTEM_CSI_PORT1_ID,
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INPUT_SYSTEM_CSI_PORT2_ID,
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INPUT_SYSTEM_PIXELGEN_PORT0_ID,
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INPUT_SYSTEM_PIXELGEN_PORT1_ID,
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INPUT_SYSTEM_PIXELGEN_PORT2_ID,
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N_INPUT_SYSTEM_INPUT_PORT_ID
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} input_system_input_port_ID_t;
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#define N_INPUT_SYSTEM_CSI_PORT 3
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typedef enum {
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ISYS2401_DMA_CHANNEL_0 = 0,
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ISYS2401_DMA_CHANNEL_1,
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ISYS2401_DMA_CHANNEL_2,
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ISYS2401_DMA_CHANNEL_3,
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ISYS2401_DMA_CHANNEL_4,
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ISYS2401_DMA_CHANNEL_5,
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ISYS2401_DMA_CHANNEL_6,
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ISYS2401_DMA_CHANNEL_7,
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ISYS2401_DMA_CHANNEL_8,
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ISYS2401_DMA_CHANNEL_9,
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ISYS2401_DMA_CHANNEL_10,
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ISYS2401_DMA_CHANNEL_11,
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N_ISYS2401_DMA_CHANNEL
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} isys2401_dma_channel;
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#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
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