// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "ia_css_mipi.h"
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#include "sh_css_mipi.h"
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#include <type_support.h>
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#include "system_global.h"
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#include "ia_css_err.h"
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#include "ia_css_pipe.h"
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#include "ia_css_stream_format.h"
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#include "sh_css_stream_format.h"
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#include "ia_css_stream_public.h"
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#include "ia_css_frame_public.h"
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#include "ia_css_input_port.h"
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#include "ia_css_debug.h"
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#include "sh_css_struct.h"
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#include "sh_css_defs.h"
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#include "sh_css_sp.h" /* sh_css_update_host2sp_mipi_frame sh_css_update_host2sp_num_mipi_frames ... */
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#include "sw_event_global.h" /* IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY */
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static u32
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ref_count_mipi_allocation[N_CSI_PORTS]; /* Initialized in mipi_init */
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int
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ia_css_mipi_frame_specify(const unsigned int size_mem_words,
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const bool contiguous) {
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int err = 0;
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my_css.size_mem_words = size_mem_words;
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(void)contiguous;
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return err;
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}
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/*
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* Check if a source port or TPG/PRBS ID is valid
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*/
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static bool ia_css_mipi_is_source_port_valid(struct ia_css_pipe *pipe,
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unsigned int *pport)
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{
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bool ret = true;
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unsigned int port = 0;
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unsigned int max_ports = 0;
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switch (pipe->stream->config.mode) {
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case IA_CSS_INPUT_MODE_BUFFERED_SENSOR:
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port = (unsigned int)pipe->stream->config.source.port.port;
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max_ports = N_CSI_PORTS;
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break;
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case IA_CSS_INPUT_MODE_TPG:
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port = (unsigned int)pipe->stream->config.source.tpg.id;
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max_ports = N_CSS_TPG_IDS;
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break;
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case IA_CSS_INPUT_MODE_PRBS:
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port = (unsigned int)pipe->stream->config.source.prbs.id;
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max_ports = N_CSS_PRBS_IDS;
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break;
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default:
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assert(false);
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ret = false;
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break;
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}
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if (ret) {
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assert(port < max_ports);
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if (port >= max_ports)
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ret = false;
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}
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*pport = port;
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return ret;
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}
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/* Assumptions:
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* - A line is multiple of 4 bytes = 1 word.
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* - Each frame has SOF and EOF (each 1 word).
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* - Each line has format header and optionally SOL and EOL (each 1 word).
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* - Odd and even lines of YUV420 format are different in bites per pixel size.
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* - Custom size of embedded data.
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* -- Interleaved frames are not taken into account.
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* -- Lines are multiples of 8B, and not necessary of (custom 3B, or 7B
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* etc.).
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* Result is given in DDR mem words, 32B or 256 bits
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*/
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int
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ia_css_mipi_frame_calculate_size(const unsigned int width,
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const unsigned int height,
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const enum atomisp_input_format format,
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const bool hasSOLandEOL,
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const unsigned int embedded_data_size_words,
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unsigned int *size_mem_words) {
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int err = 0;
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unsigned int bits_per_pixel = 0;
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unsigned int even_line_bytes = 0;
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unsigned int odd_line_bytes = 0;
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unsigned int words_per_odd_line = 0;
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unsigned int words_for_first_line = 0;
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unsigned int words_per_even_line = 0;
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unsigned int mem_words_per_even_line = 0;
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unsigned int mem_words_per_odd_line = 0;
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unsigned int mem_words_for_first_line = 0;
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unsigned int mem_words_for_EOF = 0;
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unsigned int mem_words = 0;
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unsigned int width_padded = width;
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#if defined(ISP2401)
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/* The changes will be reverted as soon as RAW
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* Buffers are deployed by the 2401 Input System
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* in the non-continuous use scenario.
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*/
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width_padded += (2 * ISP_VEC_NELEMS);
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#endif
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IA_CSS_ENTER("padded_width=%d, height=%d, format=%d, hasSOLandEOL=%d, embedded_data_size_words=%d\n",
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width_padded, height, format, hasSOLandEOL, embedded_data_size_words);
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switch (format)
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{
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case ATOMISP_INPUT_FORMAT_RAW_6: /* 4p, 3B, 24bits */
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bits_per_pixel = 6;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_7: /* 8p, 7B, 56bits */
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bits_per_pixel = 7;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_8: /* 1p, 1B, 8bits */
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case ATOMISP_INPUT_FORMAT_BINARY_8: /* 8bits, TODO: check. */
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case ATOMISP_INPUT_FORMAT_YUV420_8: /* odd 2p, 2B, 16bits, even 2p, 4B, 32bits */
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bits_per_pixel = 8;
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_10: /* odd 4p, 5B, 40bits, even 4p, 10B, 80bits */
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case ATOMISP_INPUT_FORMAT_RAW_10: /* 4p, 5B, 40bits */
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#if !defined(HAS_NO_PACKED_RAW_PIXELS)
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/* The changes will be reverted as soon as RAW
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* Buffers are deployed by the 2401 Input System
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* in the non-continuous use scenario.
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*/
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bits_per_pixel = 10;
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#else
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bits_per_pixel = 16;
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#endif
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: /* 2p, 3B, 24bits */
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case ATOMISP_INPUT_FORMAT_RAW_12: /* 2p, 3B, 24bits */
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bits_per_pixel = 12;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_14: /* 4p, 7B, 56bits */
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bits_per_pixel = 14;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_444: /* 1p, 2B, 16bits */
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case ATOMISP_INPUT_FORMAT_RGB_555: /* 1p, 2B, 16bits */
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case ATOMISP_INPUT_FORMAT_RGB_565: /* 1p, 2B, 16bits */
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case ATOMISP_INPUT_FORMAT_YUV422_8: /* 2p, 4B, 32bits */
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bits_per_pixel = 16;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_666: /* 4p, 9B, 72bits */
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bits_per_pixel = 18;
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break;
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case ATOMISP_INPUT_FORMAT_YUV422_10: /* 2p, 5B, 40bits */
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bits_per_pixel = 20;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_888: /* 1p, 3B, 24bits */
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bits_per_pixel = 24;
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_16: /* Not supported */
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case ATOMISP_INPUT_FORMAT_YUV422_16: /* Not supported */
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case ATOMISP_INPUT_FORMAT_RAW_16: /* TODO: not specified in MIPI SPEC, check */
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default:
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return -EINVAL;
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}
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odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */
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/* Even lines for YUV420 formats are double in bits_per_pixel. */
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if (format == ATOMISP_INPUT_FORMAT_YUV420_8
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|| format == ATOMISP_INPUT_FORMAT_YUV420_10
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|| format == ATOMISP_INPUT_FORMAT_YUV420_16)
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{
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even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >>
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3; /* ceil ( bits per line / 8) */
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} else
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{
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even_line_bytes = odd_line_bytes;
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}
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/* a frame represented in memory: ()- optional; data - payload words.
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* addr 0 1 2 3 4 5 6 7:
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* first SOF (SOL) PACK_H data data data data data
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* data data data data data data data data
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* ...
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* data data 0 0 0 0 0 0
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* second (EOL) (SOL) PACK_H data data data data data
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* data data data data data data data data
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* ...
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* data data 0 0 0 0 0 0
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* ...
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* last (EOL) EOF 0 0 0 0 0 0
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*
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* Embedded lines are regular lines stored before the first and after
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* payload lines.
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*/
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words_per_odd_line = (odd_line_bytes + 3) >> 2;
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/* ceil(odd_line_bytes/4); word = 4 bytes */
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words_per_even_line = (even_line_bytes + 3) >> 2;
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words_for_first_line = words_per_odd_line + 2 + (hasSOLandEOL ? 1 : 0);
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/* + SOF +packet header + optionally (SOL), but (EOL) is not in the first line */
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words_per_odd_line += (1 + (hasSOLandEOL ? 2 : 0));
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/* each non-first line has format header, and optionally (SOL) and (EOL). */
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words_per_even_line += (1 + (hasSOLandEOL ? 2 : 0));
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mem_words_per_odd_line = (words_per_odd_line + 7) >> 3;
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/* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */
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mem_words_for_first_line = (words_for_first_line + 7) >> 3;
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mem_words_per_even_line = (words_per_even_line + 7) >> 3;
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mem_words_for_EOF = 1; /* last line consisit of the optional (EOL) and EOF */
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mem_words = ((embedded_data_size_words + 7) >> 3) +
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mem_words_for_first_line +
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(((height + 1) >> 1) - 1) * mem_words_per_odd_line +
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/* ceil (height/2) - 1 (first line is calculated separatelly) */
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(height >> 1) * mem_words_per_even_line + /* floor(height/2) */
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mem_words_for_EOF;
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*size_mem_words = mem_words; /* ceil(words/8); mem word is 32B = 8words. */
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/* Check if the above is still needed. */
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IA_CSS_LEAVE_ERR(err);
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return err;
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}
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#if !defined(ISP2401)
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int
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ia_css_mipi_frame_enable_check_on_size(const enum mipi_port_id port,
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const unsigned int size_mem_words) {
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u32 idx;
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int err = -EBUSY;
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OP___assert(port < N_CSI_PORTS);
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OP___assert(size_mem_words != 0);
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for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT &&
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my_css.mipi_sizes_for_check[port][idx] != 0;
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idx++) /* do nothing */
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{
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}
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if (idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT)
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{
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my_css.mipi_sizes_for_check[port][idx] = size_mem_words;
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err = 0;
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}
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return err;
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}
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#endif
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void
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mipi_init(void)
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{
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unsigned int i;
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for (i = 0; i < N_CSI_PORTS; i++)
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ref_count_mipi_allocation[i] = 0;
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}
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int
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calculate_mipi_buff_size(
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struct ia_css_stream_config *stream_cfg,
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unsigned int *size_mem_words) {
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#if !defined(ISP2401)
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int err = -EINVAL;
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(void)stream_cfg;
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(void)size_mem_words;
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#else
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unsigned int width;
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unsigned int height;
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enum atomisp_input_format format;
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bool pack_raw_pixels;
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unsigned int width_padded;
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unsigned int bits_per_pixel = 0;
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unsigned int even_line_bytes = 0;
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unsigned int odd_line_bytes = 0;
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unsigned int words_per_odd_line = 0;
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unsigned int words_per_even_line = 0;
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unsigned int mem_words_per_even_line = 0;
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unsigned int mem_words_per_odd_line = 0;
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unsigned int mem_words_per_buff_line = 0;
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unsigned int mem_words_per_buff = 0;
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int err = 0;
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/**
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* zhengjie.lu@intel.com
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*
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* NOTE
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* - In the struct "ia_css_stream_config", there
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* are two members: "input_config" and "isys_config".
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* Both of them provide the same information, e.g.
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* input_res and format.
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*
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* Question here is that: which one shall be used?
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*/
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width = stream_cfg->input_config.input_res.width;
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height = stream_cfg->input_config.input_res.height;
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format = stream_cfg->input_config.format;
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pack_raw_pixels = stream_cfg->pack_raw_pixels;
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/* end of NOTE */
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/**
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* zhengjie.lu@intel.com
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*
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* NOTE
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* - The following code is derived from the
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* existing code "ia_css_mipi_frame_calculate_size()".
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*
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* Question here is: why adding "2 * ISP_VEC_NELEMS"
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* to "width_padded", but not making "width_padded"
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* aligned with "2 * ISP_VEC_NELEMS"?
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*/
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/* The changes will be reverted as soon as RAW
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* Buffers are deployed by the 2401 Input System
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* in the non-continuous use scenario.
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*/
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width_padded = width + (2 * ISP_VEC_NELEMS);
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/* end of NOTE */
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IA_CSS_ENTER("padded_width=%d, height=%d, format=%d\n",
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width_padded, height, format);
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bits_per_pixel = sh_css_stream_format_2_bits_per_subpixel(format);
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bits_per_pixel =
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(format == ATOMISP_INPUT_FORMAT_RAW_10 && pack_raw_pixels) ? bits_per_pixel : 16;
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if (bits_per_pixel == 0)
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return -EINVAL;
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odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */
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/* Even lines for YUV420 formats are double in bits_per_pixel. */
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if (format == ATOMISP_INPUT_FORMAT_YUV420_8
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|| format == ATOMISP_INPUT_FORMAT_YUV420_10)
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{
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even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >>
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3; /* ceil ( bits per line / 8) */
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} else
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{
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even_line_bytes = odd_line_bytes;
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}
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words_per_odd_line = (odd_line_bytes + 3) >> 2;
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/* ceil(odd_line_bytes/4); word = 4 bytes */
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words_per_even_line = (even_line_bytes + 3) >> 2;
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mem_words_per_odd_line = (words_per_odd_line + 7) >> 3;
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/* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */
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mem_words_per_even_line = (words_per_even_line + 7) >> 3;
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mem_words_per_buff_line =
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(mem_words_per_odd_line > mem_words_per_even_line) ? mem_words_per_odd_line : mem_words_per_even_line;
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mem_words_per_buff = mem_words_per_buff_line * height;
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*size_mem_words = mem_words_per_buff;
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IA_CSS_LEAVE_ERR(err);
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#endif
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return err;
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}
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static bool buffers_needed(struct ia_css_pipe *pipe)
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{
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if (!IS_ISP2401) {
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if (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR)
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return true;
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else
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return false;
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}
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if (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR ||
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pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG ||
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pipe->stream->config.mode == IA_CSS_INPUT_MODE_PRBS)
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return true;
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return false;
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}
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int
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allocate_mipi_frames(struct ia_css_pipe *pipe,
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struct ia_css_stream_info *info) {
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int err = -EINVAL;
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unsigned int port;
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) enter:\n", pipe);
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assert(pipe);
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assert(pipe->stream);
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if ((!pipe) || (!pipe->stream))
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{
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) exit: pipe or stream is null.\n",
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pipe);
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return -EINVAL;
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}
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#ifdef ISP2401
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if (pipe->stream->config.online)
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{
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) exit: no buffers needed for 2401 pipe mode.\n",
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pipe);
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return 0;
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}
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#endif
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if (!buffers_needed(pipe)) {
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) exit: no buffers needed for pipe mode.\n",
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pipe);
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return 0; /* AM TODO: Check */
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}
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if (!IS_ISP2401) {
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port = (unsigned int)pipe->stream->config.source.port.port;
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} else {
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/* Returns true if port is valid. So, invert it */
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err = !ia_css_mipi_is_source_port_valid(pipe, &port);
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}
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assert(port < N_CSI_PORTS);
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if ((!IS_ISP2401 && port >= N_CSI_PORTS) ||
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(IS_ISP2401 && err)) {
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) exit: error: port is not correct (port=%d).\n",
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pipe, port);
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return -EINVAL;
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}
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#ifdef ISP2401
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err = calculate_mipi_buff_size(
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&pipe->stream->config,
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&my_css.mipi_frame_size[port]);
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#endif
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#if !defined(ISP2401)
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if (ref_count_mipi_allocation[port] != 0)
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{
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) exit: already allocated for this port (port=%d).\n",
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pipe, port);
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return 0;
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}
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#else
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/* 2401 system allows multiple streams to use same physical port. This is not
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* true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution.
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* TODO AM: Once that is changed (removed) this code should be removed as well.
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* In that case only 2400 related code should remain.
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*/
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if (ref_count_mipi_allocation[port] != 0)
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{
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ref_count_mipi_allocation[port]++;
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p) leave: nothing to do, already allocated for this port (port=%d).\n",
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pipe, port);
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return 0;
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}
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#endif
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ref_count_mipi_allocation[port]++;
|
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/* AM TODO: mipi frames number should come from stream struct. */
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my_css.num_mipi_frames[port] = NUM_MIPI_FRAMES_PER_STREAM;
|
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/* Incremental allocation (per stream), not for all streams at once. */
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{ /* limit the scope of i,j */
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unsigned int i, j;
|
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for (i = 0; i < my_css.num_mipi_frames[port]; i++)
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{
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/* free previous frame */
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if (my_css.mipi_frames[port][i]) {
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ia_css_frame_free(my_css.mipi_frames[port][i]);
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my_css.mipi_frames[port][i] = NULL;
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}
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/* check if new frame is needed */
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if (i < my_css.num_mipi_frames[port]) {
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/* allocate new frame */
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err = ia_css_frame_allocate_with_buffer_size(
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&my_css.mipi_frames[port][i],
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my_css.mipi_frame_size[port] * HIVE_ISP_DDR_WORD_BYTES,
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false);
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if (err) {
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for (j = 0; j < i; j++) {
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if (my_css.mipi_frames[port][j]) {
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ia_css_frame_free(my_css.mipi_frames[port][j]);
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my_css.mipi_frames[port][j] = NULL;
|
}
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}
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
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"allocate_mipi_frames(%p, %d) exit: error: allocation failed.\n",
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pipe, port);
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return err;
|
}
|
}
|
if (info->metadata_info.size > 0) {
|
/* free previous metadata buffer */
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if (my_css.mipi_metadata[port][i]) {
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ia_css_metadata_free(my_css.mipi_metadata[port][i]);
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my_css.mipi_metadata[port][i] = NULL;
|
}
|
/* check if need to allocate a new metadata buffer */
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if (i < my_css.num_mipi_frames[port]) {
|
/* allocate new metadata buffer */
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my_css.mipi_metadata[port][i] = ia_css_metadata_allocate(&info->metadata_info);
|
if (!my_css.mipi_metadata[port][i]) {
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ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"allocate_mipi_metadata(%p, %d) failed.\n",
|
pipe, port);
|
return err;
|
}
|
}
|
}
|
}
|
}
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"allocate_mipi_frames(%p) exit:\n", pipe);
|
|
return err;
|
}
|
|
int
|
free_mipi_frames(struct ia_css_pipe *pipe) {
|
int err = -EINVAL;
|
unsigned int port;
|
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) enter:\n", pipe);
|
|
/* assert(pipe != NULL); TEMP: TODO: Should be assert only. */
|
if (pipe)
|
{
|
assert(pipe->stream);
|
if ((!pipe) || (!pipe->stream)) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) exit: error: pipe or stream is null.\n",
|
pipe);
|
return -EINVAL;
|
}
|
|
if (!buffers_needed(pipe)) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) exit: error: wrong mode.\n",
|
pipe);
|
return err;
|
}
|
|
if (!IS_ISP2401) {
|
port = (unsigned int)pipe->stream->config.source.port.port;
|
} else {
|
/* Returns true if port is valid. So, invert it */
|
err = !ia_css_mipi_is_source_port_valid(pipe, &port);
|
}
|
|
assert(port < N_CSI_PORTS);
|
|
if ((!IS_ISP2401 && port >= N_CSI_PORTS) ||
|
(IS_ISP2401 && err)) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p, %d) exit: error: pipe port is not correct.\n",
|
pipe, port);
|
return err;
|
}
|
|
if (ref_count_mipi_allocation[port] > 0) {
|
#if !defined(ISP2401)
|
assert(ref_count_mipi_allocation[port] == 1);
|
if (ref_count_mipi_allocation[port] != 1) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) exit: error: wrong ref_count (ref_count=%d).\n",
|
pipe, ref_count_mipi_allocation[port]);
|
return err;
|
}
|
#endif
|
|
ref_count_mipi_allocation[port]--;
|
|
if (ref_count_mipi_allocation[port] == 0) {
|
/* no streams are using this buffer, so free it */
|
unsigned int i;
|
|
for (i = 0; i < my_css.num_mipi_frames[port]; i++) {
|
if (my_css.mipi_frames[port][i]) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(port=%d, num=%d).\n", port, i);
|
ia_css_frame_free(my_css.mipi_frames[port][i]);
|
my_css.mipi_frames[port][i] = NULL;
|
}
|
if (my_css.mipi_metadata[port][i]) {
|
ia_css_metadata_free(my_css.mipi_metadata[port][i]);
|
my_css.mipi_metadata[port][i] = NULL;
|
}
|
}
|
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) exit (deallocated).\n", pipe);
|
}
|
#if defined(ISP2401)
|
else {
|
/* 2401 system allows multiple streams to use same physical port. This is not
|
* true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution.
|
* TODO AM: Once that is changed (removed) this code should be removed as well.
|
* In that case only 2400 related code should remain.
|
*/
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(%p) leave: nothing to do, other streams still use this port (port=%d).\n",
|
pipe, port);
|
}
|
#endif
|
}
|
} else /* pipe ==NULL */
|
{
|
/* AM TEMP: free-ing all mipi buffers just like a legacy code. */
|
for (port = CSI_PORT0_ID; port < N_CSI_PORTS; port++) {
|
unsigned int i;
|
|
for (i = 0; i < my_css.num_mipi_frames[port]; i++) {
|
if (my_css.mipi_frames[port][i]) {
|
ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
|
"free_mipi_frames(port=%d, num=%d).\n", port, i);
|
ia_css_frame_free(my_css.mipi_frames[port][i]);
|
my_css.mipi_frames[port][i] = NULL;
|
}
|
if (my_css.mipi_metadata[port][i]) {
|
ia_css_metadata_free(my_css.mipi_metadata[port][i]);
|
my_css.mipi_metadata[port][i] = NULL;
|
}
|
}
|
ref_count_mipi_allocation[port] = 0;
|
}
|
}
|
return 0;
|
}
|
|
int
|
send_mipi_frames(struct ia_css_pipe *pipe) {
|
int err = -EINVAL;
|
unsigned int i;
|
#ifndef ISP2401
|
unsigned int port;
|
#else
|
unsigned int port = 0;
|
#endif
|
|
IA_CSS_ENTER_PRIVATE("pipe=%p", pipe);
|
|
assert(pipe);
|
assert(pipe->stream);
|
if (!pipe || !pipe->stream)
|
{
|
IA_CSS_ERROR("pipe or stream is null");
|
return -EINVAL;
|
}
|
|
/* multi stream video needs mipi buffers */
|
/* nothing to be done in other cases. */
|
if (!buffers_needed(pipe)) {
|
IA_CSS_LOG("nothing to be done for this mode");
|
return 0;
|
/* TODO: AM: maybe this should be returning an error. */
|
}
|
|
if (!IS_ISP2401) {
|
port = (unsigned int)pipe->stream->config.source.port.port;
|
} else {
|
/* Returns true if port is valid. So, invert it */
|
err = !ia_css_mipi_is_source_port_valid(pipe, &port);
|
}
|
|
assert(port < N_CSI_PORTS);
|
|
if ((!IS_ISP2401 && port >= N_CSI_PORTS) ||
|
(IS_ISP2401 && err)) {
|
IA_CSS_ERROR("send_mipi_frames(%p) exit: invalid port specified (port=%d).\n",
|
pipe, port);
|
return err;
|
}
|
|
/* Hand-over the SP-internal mipi buffers */
|
for (i = 0; i < my_css.num_mipi_frames[port]; i++)
|
{
|
/* Need to include the ofset for port. */
|
sh_css_update_host2sp_mipi_frame(port * NUM_MIPI_FRAMES_PER_STREAM + i,
|
my_css.mipi_frames[port][i]);
|
sh_css_update_host2sp_mipi_metadata(port * NUM_MIPI_FRAMES_PER_STREAM + i,
|
my_css.mipi_metadata[port][i]);
|
}
|
sh_css_update_host2sp_num_mipi_frames(my_css.num_mipi_frames[port]);
|
|
/**********************************
|
* Send an event to inform the SP
|
* that all MIPI frames are passed.
|
**********************************/
|
if (!sh_css_sp_is_running())
|
{
|
/* SP is not running. The queues are not valid */
|
IA_CSS_ERROR("sp is not running");
|
return err;
|
}
|
|
ia_css_bufq_enqueue_psys_event(
|
IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY,
|
(uint8_t)port,
|
(uint8_t)my_css.num_mipi_frames[port],
|
0 /* not used */);
|
IA_CSS_LEAVE_ERR_PRIVATE(0);
|
return 0;
|
}
|
